Physical Design
The physical design of the unit has been achieved by the usage of a
script. As for the synthesis, this script is in charge of preparing the
environment and start the real script for the physical design.
This step is very well known as a computing intensive step, even more
than the synthesis since the granularity of details is bigger than the
one in the synthesis. Therefore, for boosting-up the performance the
script automatically sets the usage of six threads instead of only
one.
Nevertheless the variety in the design space, only a subset of them has been chosen for being placed on a die. In particular the unconstrained design, the minimum area and a 1% more of the clock frequency (wrt to the non-constrained design frequency) and only the 10% more of the clock frequency designs. It is worth to mention that the physical design does not use the RTL description but it uses the gate-level netlist of the RTL, produced by the synthesis.
In the following pages, results are presented as images of the design on
the same die.
As first result of physical design, it is worth to present the ameba
view. It distinguish between the control unit and the datapath of the
DLX. As it can be seen, the area occupied by the control unit is always the same.
Moreover, from Figures it may seem that the pins are overlapping. However, this is not the case, it is only a matter of image resolution. Specifically, the pins on the top and right side (respectively for the IRAM and DRAM) are overlapped but on different level of the die. On the other hand, all the control signals from/to memories, clock and reset signals are on the bottom of the left corner.
Unconstrained design
10% more on clock frequency
1% more on clock frequency and minimum area
An important aspect is how the datapath area is changing, having in mind
the boundaries of datapath from Figures
and looking at Figures.
From A to C there is a consistent area reduction, the area is reducing
by a factor of almost 2, this is mainly due to the area constraint
and/or the relaxation on clock constraint. Comparing the Figure
with the Figure,
even if there is a slight increase in the clock frequency, the synthesis
strategies are different (it goes from a naive synthesis to a synthesis
in which better optimization efforts are done in order to reduce design
metrics).
Therefore, even with a bigger clock frequency the final result is better
than the non-constrained synthesis. The only difference with Figure
is the constraint on finding the design with the minimum area and a
lower increase in the clock frequency(only 1%). The mix of those
constrains has leaded to a further reduction in the area on the die.
Unconstrained design
10% more on clock frequency
1% more on clock frequency and minumum area