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Welcome to the DLX_project wiki! This is a markdown mirror of the latex report.

Introduction

The DeLuXe (aka DLX) is a RISC processor architecture designed by John L. Hennessy and David A. Patterson. It is a modernized and simplified 32-bit load/store big endian architecture of the MIPS CPU, primarily intended for teaching purposes.

In the following pages the ASIC design flow has been applied for developing the DLX processor. Starting from the basic requirements of DLX, it has been developed accordingly with basic features, i.e. the pipeline and the basic instruction set. As extension of ISA, the integer multiplication has been added to the basic instruction set. For doing that, the Booth’s multiplier studied during the course and developed during the laboratories has been pipelined in order to obtain a pipelined multiplier on eight clock cycles.
An important aspect of Digital Desing, in the design step, is to verify the functional behavior of the components. In order to do that, test benches in System Verilog have been used (resorting to a mixed language simulation) in order to maximize the efficiency of testing (resorting to automatic techniques) and speeding up the development time. It has also allowed to removed bugs during the early functional tests of the stages composing the pipeline by the mean of defining temporal properties on signals. Moreover, at the end, another test bench using the Universal Verification Methodology has been developed, which is a de facto standard in the industry for Functional Verification Testing of Integrated Circuit.

As last step of the design flow, the design is synthesized with different approaches in order to move the processor in different design point of the space (area, clock frequency and power). After that, a subset of the synthesized designs is physically designed. Starting with the routing of the power supply system and ending with the placed and routed of the actual transistors (layout design phase).