Skip to content

farhanrahman/VHDLProject

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 
 
 
 
 
 
 
 
 

Repository files navigation

This is the VHDL coursework for the EEE/ISE/EIE third year course VHDL and Logic Synthesis in the spring term. The coursework looks into building a Vector Display Processor which takes in commands and draws pixels onto a screen.

The hardware is split into two blocks:

  1. Draw Block (DB): Decodes commands and sends them to the Ram Control Block.

  2. Ram Control Block (RCB): Takes decoded commands from Draw Block and draws pixels onto the screen

More information about the blocks can be found in the doc folder for the respective block folders

contributers:

1) Jonathan Ely (jjonnnyy)
2) Farhan Rahman (farhanrahman)

About

No description, website, or topics provided.

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published

Languages