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README.md

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This is the VHDL coursework for the EEE/ISE/EIE third year course VHDL and Logic Synthesis in the spring term. The coursework looks into building a Vector Display Processor which takes in commands and draws pixels onto a screen.

The hardware is split into two blocks:

  1. Draw Block (DB): Decodes commands and sends them to the Ram Control Block.

  2. Ram Control Block (RCB): Takes decoded commands from Draw Block and draws pixels onto the screen

More information about the blocks can be found in the doc folder for the respective block folders

contributers:

1) Jonathan Ely (jjonnnyy)
2) Farhan Rahman (farhanrahman)