fix resynthesis class name

openlane/steps/pyosys.py

@@ -604,7 +604,7 @@ class Synthesis(SynthesisCommon):
 
 
 @Step.factory.register()
-class Resynthesize(SynthesisCommon):
+class Resynthesis(SynthesisCommon):
     """
     Like ``Synthesis``, but operates on the input netlist instead of RTL files.
     Useful to process/elaborate on netlists generated by tools other than Yosys.