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Issues: efabless/openlane2

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#201 opened Oct 2, 2023 by donn
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Issues list

Versioning for dev branch
#602 opened Nov 21, 2024 by kareefardi
Allow dynamic registration of new DesignFormats ✨ enhancement New feature or request
#601 opened Nov 21, 2024 by donn 3.0.0
Portable States ⛓️‍💥 breaking change This issue may require a change to OpenLane's API ✨ enhancement New feature or request
#600 opened Nov 21, 2024 by donn 3.0.0
Unify common.Path and pathlib.Path ⛓️‍💥 breaking change This issue may require a change to OpenLane's API ✨ enhancement New feature or request
#599 opened Nov 21, 2024 by donn 3.0.0
Synthesis no longer works via Google Colab 🐞 bug Something isn't working workaround This issue has an end-user workaround
#590 opened Oct 21, 2024 by ajkourabi
Verilator doesn't recognize macros
#579 opened Oct 12, 2024 by smunaut
SDC as single source of truth for clock info ⛓️‍💥 breaking change This issue may require a change to OpenLane's API ✨ enhancement New feature or request
#572 opened Oct 7, 2024 by donn 3.0.0
Checking the results problem 🐞 bug Something isn't working
#570 opened Oct 6, 2024 by ripudamank2
openlane2 non going through --smoke-test 🐞 bug Something isn't working 💬 waiting on op This issue requires more information from its original creator
#569 opened Oct 5, 2024 by ctalar
Add missing metrics to library.py ✨ enhancement New feature or request
#567 opened Oct 3, 2024 by kareefardi
Explore integrating DRiLLS for ABC scripts ✨ enhancement New feature or request
#559 opened Sep 23, 2024 by donn
Explore OpenROAD local resynthesis ⛔️ blocked This issue or PR is pending an issue with an underlying utility ✨ enhancement New feature or request
#558 opened Sep 23, 2024 by donn
Support for PDKs without TAP / ENDCAP cells ⛓️‍💥 breaking change This issue may require a change to OpenLane's API
#554 opened Sep 21, 2024 by smunaut 3.0.0
Warning in the PDK LEF files ⛔️ blocked This issue or PR is pending an issue with an underlying utility ✨ enhancement New feature or request
#550 opened Sep 18, 2024 by kareefardi
Separate corner for Synthesis ✨ enhancement New feature or request
#546 opened Sep 5, 2024 by donn 3.0.0
Inject custom Verilog into the flow ⛓️‍💥 breaking change This issue may require a change to OpenLane's API
#543 opened Sep 4, 2024 by mole99
Better antenna repair ✨ enhancement New feature or request
#542 opened Sep 4, 2024 by kareefardi 3.0.0
PL_MAX_DISPLACEMENT_{X,Y} set atrociously high in both OpenLanes ⛓️‍💥 breaking change This issue may require a change to OpenLane's API ✨ enhancement New feature or request
#541 opened Sep 1, 2024 by donn 3.0.0
Move SIGNAL_WIRE_RC_LAYERS, CLOCK_WIRE_RC_LAYERS to the relevant steps ⛓️‍💥 breaking change This issue may require a change to OpenLane's API ✨ enhancement New feature or request
#540 opened Aug 29, 2024 by donn 3.0.0
Point scripts to get VDD_PIN_VOLTAGE from lib file ⛓️‍💥 breaking change This issue may require a change to OpenLane's API ✨ enhancement New feature or request
#539 opened Aug 29, 2024 by donn 3.0.0
ProTip! Follow long discussions with comments:>50.