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Verilog: clarify method signatures #356

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merged 2 commits into from
Jan 31, 2024
Merged

Verilog: clarify method signatures #356

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0acb673
Verilog: set module value in typecheck()
kroening Jan 28, 2024
54d941d
Verilog: clarify signature of verilog_typecheckt::check_module_ports
kroening Jan 28, 2024
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6 changes: 2 additions & 4 deletions src/verilog/verilog_interfaces.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ void verilog_typecheckt::module_interface(
interface_module_item(module_item);

// Check the typing of the ports
check_module_ports(module_source);
check_module_ports(module_source.ports());
}

/*******************************************************************\
Expand All @@ -51,10 +51,8 @@ Function: verilog_typecheckt::check_module_ports
\*******************************************************************/

void verilog_typecheckt::check_module_ports(
const verilog_module_sourcet &module_source)
const verilog_module_sourcet::port_listt &module_ports)
{
const auto &module_ports = module_source.ports();

auto &ports = module_symbol.type.add(ID_ports).get_sub();
ports.resize(module_ports.size());
std::map<irep_idt, unsigned> port_names;
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8 changes: 4 additions & 4 deletions src/verilog/verilog_typecheck.cpp
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Expand Up @@ -1604,9 +1604,6 @@ void verilog_typecheckt::convert_statements(
// typecheck the new module items
for(auto &item : verilog_module_expr.module_items())
convert_module_item(item);

// store the module expression in module_symbol.value
module_symbol.value = std::move(verilog_module_expr);
}

/*******************************************************************\
Expand Down Expand Up @@ -1674,8 +1671,11 @@ void verilog_typecheckt::typecheck()

auto verilog_module_expr = elaborate_generate_constructs(module_source);

// Now typecheck the statements.
// Now typecheck the generated statements.
convert_statements(verilog_module_expr);

// store the module expression in module_symbol.value
module_symbol.value = std::move(verilog_module_expr);
}

/*******************************************************************\
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2 changes: 1 addition & 1 deletion src/verilog/verilog_typecheck.h
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Expand Up @@ -111,7 +111,7 @@ class verilog_typecheckt:

// interfaces
void module_interface(const verilog_module_sourcet &);
void check_module_ports(const verilog_module_sourcet &);
void check_module_ports(const verilog_module_sourcet::port_listt &);
void interface_module_decl(const class verilog_declt &);
void interface_function_or_task_decl(const class verilog_declt &);
void interface_inst(const verilog_inst_baset &);
Expand Down