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Verilog: clarify method signatures #356

Merged
merged 2 commits into from
Jan 31, 2024
Merged

Verilog: clarify method signatures #356

merged 2 commits into from
Jan 31, 2024

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kroening
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To clarify the side effect of the typecheck() method, the value of the module symbol is now set there.

@kroening
Verilog: set module value in typecheck()
0acb673 
To clarify the side effect of the typecheck() method, the value of the
module symbol is now set there.
@kroening kroening marked this pull request as ready for review January 28, 2024 02:42
@kroening
Verilog: clarify signature of verilog_typecheckt::check_module_ports
54d941d 
This method only takes the ports as input, not the full module source.
@kroening kroening changed the title Verilog: set module value in typecheck() Verilog: clarify method signatures Jan 28, 2024
@tautschnig tautschnig merged commit 80245d3 into main Jan 31, 2024
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@tautschnig tautschnig deleted the verilog_module_expr branch January 31, 2024 11:41
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@tautschnig tautschnig tautschnig approved these changes

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@kroening @tautschnig