Merge pull request #509 from diffblue/synth-part-select

Verilog: move translation of part select expressions into synthesis phase
diffblue · May 19, 2024 · 66a241c · 66a241c
2 parents 1976274 + 491a289
commit 66a241c
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diff --git a/regression/verilog/synthesis/part_select1.desc b/regression/verilog/synthesis/part_select1.desc
@@ -0,0 +1,7 @@
+CORE
+part_select1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
diff --git a/regression/verilog/synthesis/part_select1.sv b/regression/verilog/synthesis/part_select1.sv
@@ -0,0 +1,15 @@
+module main;
+
+  reg [31:0] t;
+
+  always @(*) begin
+    t = 0;
+
+    // out of bounds accesses are ignored
+    t[0:-1] = 'b10;
+
+    // should pass
+    assert(t == 1);
+  end
+
+endmodule