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Merge pull request #510 from diffblue/stable-rose-fell-changed
SystemVerilog: $stable, $rose, $fell, $changed
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regression/verilog/system-functions/stable-rose-fell-changed1.desc
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,7 @@ | ||
CORE | ||
stable-rose-fell-changed1.sv | ||
--bound 1 | ||
^EXIT=0$ | ||
^SIGNAL=0$ | ||
-- | ||
^warning: ignoring |
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regression/verilog/system-functions/stable-rose-fell-changed1.sv
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,18 @@ | ||
module main(input clk); | ||
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reg [31:0] counter = 0; | ||
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always @(posedge clk) | ||
counter++; | ||
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initial p0: assert property ($stable(counter)); | ||
initial p1: assert property (!$rose(counter)); | ||
initial p2: assert property (!$fell(counter)); | ||
initial p3: assert property (!$changed(counter)); | ||
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initial p4: assert property (##1 !$stable(counter)); | ||
initial p5: assert property (##1 $rose(counter)); | ||
initial p6: assert property (##1 !$fell(counter)); | ||
initial p7: assert property (##1 $changed(counter)); | ||
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endmodule |
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