Handle introduction of ref_typespec in UHDM/Surelog

[hs-apotell]

Handle introduction of ref_typespec in UHDM/Surelog

chipsalliance/UHDM#1022
chipsalliance/Surelog#3868

[alaindargelas]

@wsipak @kbieganski the next time you want to update Surelog, this PR needs to be merged.
Please authorize the Actions.

[kgugala]

looks like this code doesn't build, @hs-apotell can you take a look at this?

[hs-apotell]

@kgugala CI isn't pulling the latest from UHDM and Surelog.

This PR requires at least 893badb9ab9f382547b77cffaaa159f146f4f64c from UHDM and 7cb11f24f13a6fa4fc0f583d599736b6aeeddf86 from Surelog.

CI is reporting UHDM checked out 21699af32d84445ab997373e641bb734fbf34f33 and Surelog checked out at f1dfa053a04256aea769baa93d4d2e7cea5c1807 both of which aren't at head.

[pgielda]

@hs-apotell CI is not affecting which commit it takes, its the repo -- CI is just pulling the submodules in third-party: https://github.com/chipsalliance/synlig/tree/main/third_party so if you want to use a different commit you have to update your fork and push force.

[hs-apotell]

@pgielda Done! I wrongly assumed that CI was forcing a pull from Surelog master (like it does on Surelog CI). I have updated third_party/Surelog.

Can you approve a PR verification build?

[kgugala]

there seem to be some segfaults, there is some hint from ASAN in the EnumBases test:

simple_tests/EnumBases
  ▌ AddressSanitizer:DEADLYSIGNAL
  ▌ ASAN issues:
  ▌ 
  ▌ ==9326==ERROR: AddressSanitizer: SEGV on unknown address 0x000000000068 (pc 0x7f975acac11a bp 0x7ffd5a1231f0 sp 0x7ffd5a1230e0 T0)
  ▌ ==9326==Hint: address points to the zero page.
  ▌ SUMMARY: AddressSanitizer: SEGV /root/synlig/synlig/frontends/systemverilog/uhdm_ast.cc in systemverilog_plugin::UhdmAst::process_enum_typespec()
  ▌ 

[pgielda]

@hs-apotell no, we pin e.g. surelog and yosys versions (as well as other versions) and have a dependabot that tries to bump them to main. Its merged if green, but often its not (due to changes that need an implementation in the plugin or simply bugs/regressions on upstream versions of tools) so then its being figured out manually. See #2004 where the bot updates surelog but the CI fails, I assume exactly because of the changes that are needed in the plugin that you are trying to resolve here.

Surelog on the other hand has a CI that tests if it breaks compatibility with the plugin so that such changes can be detected and avoided or mentioned here when there is an API change or some other reason that requires a plugin change.

[hs-apotell]

there seem to be some segfaults, there is some hint from ASAN in the EnumBases test:

Fixed.

[hs-apotell]

Quick follow up - Doesn't look like current failure have anything to do with changes in this PR. Correct me if I am wrong.

[alain-rs]

@hs-apotell the last merged PR has all tests passing:
#1999

So this PR has issues.
Moreover the last passing PR had the Surelog version right before your merge:
#1997

[hs-apotell]

The logs with the failures are less than helpful to provide any indication of what/where it failed. I don't have a local setup to run yosys (I am on Windows platform).

Can someone spare a few moments to debug the issue locally to provide some insight into the cause of the failures?

Summary of what's attempted - All references to model objects of type typespec are now redirected thru' ref_typespec. i.e. ptr->Typespec() would now be ptr->Typespec()->Actual_typespec().

[alaindargelas]

@kgugala please add @hs-apotell as a contributor

[alaindargelas]

@hs-apotell , chipsalliance/Surelog#3872 fixed the failure on simple_AssignToUnionAndReadField,
please update Surelog in this PR.

make -C tests uhdm/yosys/test-ast TEST=simple_tests/AssignToUnionAndReadField PARSER=surelog

...
Simulating cycle 39.
Simulating cycle 40.

End of script. Logfile hash: d6346436ba, CPU: user 0.01s system 0.00s, MEM: 24.68 MB peak
Yosys 0.30+16 (git sha1 8b2a00102, gcc 11.2.0-7ubuntu2 -fPIC -Os)
Time spent: 45% 1x plugin (0 sec), 14% 2x read_uhdm (0 sec), ...
make: Leaving directory '/home/alain/synlig/tests'

[alaindargelas]

It also fixes the 2 formal failures:

~/synlig$ ./run_fv_tests.mk TEST_SUITE_DIR:=tests/simple_tests AnonymousUnion/top.sv
AnonymousUnion/top.sv
# run_yosys:       RC: 0; Usr Time: 1.941 s; Sys Time: 0.032 s; Elapsed: 1.995 s; Max RSS: 146056 kB
# run_surelog:     RC: 0; Usr Time: 1.973 s; Sys Time: 0.064 s; Elapsed: 2.052 s; Max RSS: 171832 kB
# run_equiv:       RC: 0; Usr Time: 1.239 s; Sys Time: 0.060 s; Elapsed: 1.299 s; Max RSS: 209240 kB
{'name': 'AnonymousUnion/top.sv', 'yosys': 'OK', 'sv2v_yosys': 'SKIPPED', 'surelog': 'PASS', 'sv2v_surelog': 'SKIPPED', 'user': 1.239, 'elapsed': 1.299, 'cpu': 100, 'resident': 204.336}

alain@alain-xps:~/synlig$ ./run_fv_tests.mk TEST_SUITE_DIR:=tests/simple_tests AssignToUnionAndReadField/top.sv
AssignToUnionAndReadField/top.sv
# run_yosys:       RC: 0; Usr Time: 1.890 s; Sys Time: 0.036 s; Elapsed: 1.926 s; Max RSS: 145972 kB
# run_surelog:     RC: 0; Usr Time: 1.991 s; Sys Time: 0.040 s; Elapsed: 2.031 s; Max RSS: 171504 kB
# run_equiv:       RC: 0; Usr Time: 1.270 s; Sys Time: 0.028 s; Elapsed: 1.298 s; Max RSS: 209704 kB
{'name': 'AssignToUnionAndReadField/top.sv', 'yosys': 'OK', 'sv2v_yosys': 'SKIPPED', 'surelog': 'PASS', 'sv2v_surelog': 'SKIPPED', 'user': 1.27, 'elapsed': 1.298, 'cpu': 100, 'resident': 204.789}

[alaindargelas]

@kbieganski how to run locally this test:

❌ FAIL
lowrisc:systems_custom_tiny:chip_custom_tiny_nexysvideo:0.1
 

[hs-apotell]

please update Surelog in this PR.

Done! Need someone to approve the workflows.

[alaindargelas]

Yes, hopefully @kgugala can add you as a contributor today so we can iterate over the week-end if there are still failures.

[kgugala]

@hs-apotell I've added you

[kgugala]

CI seems to be green now. @kbieganski please take look at this on Monday and review/merge.

[alaindargelas]

I reviewed this. Let's merge it, it is blocking a lot of other work

[pgielda]

I am confused, just use a branch? How is that a blocker?

[pgielda]

(@kbieganski is out of office today, he will be back on Monday and will look at it)

[alaindargelas]

I need this to be merged to my fork of this repo so I can attend to other failures. Can you accept this PR? It seems I don't have the rights to merge PR (no write access, only contributor). I work on weekends, delaying this prevent velocity. This PR is 100% correct. Or please add my rights to Write so I can merge after review which I can't now

[pgielda]

I do not have merge rights here, @kgugala can you merge?

[pgielda]

(@alaindargelas bear in mind its Friday evening here so no guarantees)

[alaindargelas]

Yes :-) Thanks guys, or @kbieganski might see and approve it.

[kgugala]

Sure, I'll merge this but I'd still prefer @kbieganski look at this and do proper public review