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update surelog const propagation #4923

Job	Run time
Build Binaries	4m 15s
Build sv2v	1m 27s
Emit Workflow Info	0s
Build Binaries (ASAN)	7m 46s
Style check	1m 8s
Upload GHA event file	7s
Parsing Tests / Surelog	20m 42s
Formal Verification Tests / simple	11m 8s
Parsing Tests / SystemVerilog Plugin	29m 30s
Formal Verification Tests / sv2v	15m 38s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	8m 1s
Formal Verification Tests / yosys	15m 37s
Large Designs Tests / Ibex (Vivado synthesis)	6m 16s
Large Designs Tests / Ibex (F4PGA synthesis)	10m 59s
Large Designs Tests / Black Parrot (synthesis)	34m 10s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	0s
Large Designs Tests / Opentitan parsing (full/top-down)	2h 21m 29s
Large Designs Tests / Opentitan parsing (quick)	1h 18m 43s
Large Designs Tests / Opentitan (synthesis)	1h 46m 10s
Large Designs Tests / VeeR-EH1 (synthesis)	6m 11s
Formal Verification Tests / Passlist Check	1m 7s
Parsing Tests / Summary Generation	1m 7s
Parsing Tests / Generate AST diff	0s
Release Package	0s
Release Package Installation Test	0s
	8h 21m 31s

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