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update surelog const propagation #4923

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update surelog const propagation

update surelog const propagation #4923

Triggered via pull request September 25, 2023 18:46
@alaindargelasalaindargelas
synchronize #2009
alaindargelas:update_surelog_const_push
Status Failure
Total duration 2h 29m 31s
Artifacts 20
This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

main.yml

on: pull_request
Matrix: build-binaries
Build sv2v
1m 27s
Build sv2v
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 8s
Style check
Upload GHA event file
7s
Upload GHA event file
Parsing Tests  /  SystemVerilog Plugin
29m 30s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 16s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
10m 59s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
0s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
1h 46m
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
6m 11s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (synthesis)
34m 10s
Large Designs Tests / Black Parrot (synthesis)
Parsing Tests  /  Surelog
20m 42s
Parsing Tests / Surelog
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
8m 1s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 7s
Parsing Tests / Summary Generation
Formal Verification Tests  /  Passlist Check
1m 7s
Formal Verification Tests / Passlist Check
Release Package
0s
Release Package
Release Package Installation Test
0s
Release Package Installation Test
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Annotations

1 error and 3 warnings
Parsing Tests / SystemVerilog Plugin
Process completed with exit code 1.
Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Artifacts

Produced during runtime
Name Size
binaries Expired
205 MB
binaries-asan Expired
1.3 GB
bp_e_bp_unicore_cfg.edif Expired
160 MB
bsg-logs Expired
80.3 MB
bsg-outputs Expired
6.99 MB
event.json Expired
27.5 KB
formal-verification-logs Expired
675 MB
formal-verification-tests-list Expired
53.1 KB
lowrisc_ibex_top_artya7_surelog_0.1.bit Expired
2.09 MB
lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif Expired
272 MB
opentitan-logs-full Expired
166 MB
opentitan-logs-quick Expired
39.6 MB
parsing_read-systemverilog_logs Expired
14.4 MB
parsing_read-systemverilog_yosys-sv Expired
324 KB
parsing_read-uhdm_logs Expired
14.2 MB
parsing_read-uhdm_yosys-sv Expired
322 KB
parsing_test-results Expired
19.7 KB
plots Expired
27.9 MB
sv2v Expired
8.3 MB
top_artya7.bit Expired
2.09 MB