main

Build(deps): Bump third_party/yosys from `6f3376c` to `384c191` #6086

Job	Run time
Build Synlig Release	16m 52s
Build Plugin	16m 45s
Build Synlig (ASAN)	6m 52s
Build Package	20m 25s
Build PySynlig	25m 8s
Build tools	10m 31s
Emit Workflow Info	0s
Style check	1m 32s
Verify README Correctness (Installation From Sources)	42m 48s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 37s
Formal Verification Tests / simple	15m 19s
Large Designs Tests / Black Parrot (ASIC synthesis)	34m 15s
Formal Verification Tests / sv2v	14m 40s
Formal Verification Tests / yosys	12m 21s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	11m 58s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	38m 8s
Large Designs Tests / Ibex (Vivado synthesis)	6m 11s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 42s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	23m 58s
Large Designs Tests / Opentitan parsing (full/top-down)	11m 59s
Large Designs Tests / Opentitan (synthesis)	58m 56s
Large Designs Tests / Opentitan parsing (quick)	5m 9s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 25s
Parsing Tests / Test read_systemverilog release	4m 22s
Parsing Tests / Test read_uhdm release	4m 3s
Parsing Tests / Test read_systemverilog plugin	4m 27s
Parsing Tests / Test read_uhdm plugin	4m 8s
Parsing Tests / Test read_systemverilog asan	35m 18s
Parsing Tests / Test read_uhdm asan	25m 1s
Parsing Tests / Generate AST diff	1m 47s
Parsing Tests / Summary Generation	1m 23s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 58m 0s

Provide feedback