Build(deps): Bump third_party/yosys from 6f3376c to 384c191
#6086
Triggered via pull request
December 4, 2024 07:20
dependabot[bot]
Status
Failure
Total duration
1h 24m 30s
Artifacts
49
main.yml
on: pull_request
Matrix: build-binaries
Build tools
10m 31s
Emit Workflow Info
0s
Style check
1m 32s
Verify README Correctness (Installation From Sources)
42m 48s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 11s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 42s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
23m 58s
Large Designs Tests
/
Opentitan (synthesis)
58m 56s
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 25s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
11m 58s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
34m 15s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
38m 8s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 37s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
1m 47s
Parsing Tests
/
Summary Generation
1m 23s
Verify README Correctness (Download And Run Release)
0s
Annotations
1 error and 4 warnings
|
Formal Verification Tests / yosys
Process completed with exit code 1.
|
|
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
|
|
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
|
|
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
|
|
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
|
Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
binaries-asan
|
292 MB |
|
|
binaries-package
|
23.2 MB |
|
|
binaries-plugin
|
41.7 MB |
|
|
binaries-pysynlig
|
651 MB |
|
|
binaries-release
|
42 MB |
|
|
bp_e_bp_unicore_cfg.edif
|
3.92 MB |
|
|
bsg-logs
|
5.57 MB |
|
|
bsg-outputs
|
1.73 MB |
|
|
formal-verification-logs-simple
|
18.8 MB |
|
|
formal-verification-logs-sv2v
|
63.1 MB |
|
|
formal-verification-logs-yosys
|
50.3 MB |
|
|
lowrisc_ibex_top_artya7_surelog_0.1.bit
|
105 KB |
|
|
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
616 KB |
|
|
opentitan-logs-full
|
4.58 MB |
|
|
opentitan-logs-quick
|
832 KB |
|
|
plots_binaries-asan
|
48.8 KB |
|
|
plots_binaries-package
|
143 KB |
|
|
plots_binaries-plugin
|
123 KB |
|
|
plots_binaries-pysynlig
|
169 KB |
|
|
plots_binaries-release
|
118 KB |
|
|
plots_blackparrot_synth_asic
|
208 KB |
|
|
plots_blackparrot_synth_xilinx
|
83.6 KB |
|
|
plots_blackparrot_synth_xilinx_python
|
221 KB |
|
|
plots_build_tools
|
78.1 KB |
|
|
plots_formal_verification_simple
|
103 KB |
|
|
plots_formal_verification_sv2v
|
99 KB |
|
|
plots_formal_verification_yosys
|
83.9 KB |
|
|
plots_ibex_synth
|
44.9 KB |
|
|
plots_ibex_synth_f4pga
|
83.5 KB |
|
|
plots_opentitan_9d82960888_synth
|
136 KB |
|
|
plots_opentitan_parse_report_full
|
81.2 KB |
|
|
plots_opentitan_parse_report_quick
|
37.5 KB |
|
|
plots_opentitan_synth
|
318 KB |
|
|
plots_tests_asan_read_systemverilog
|
220 KB |
|
|
plots_tests_asan_read_uhdm
|
161 KB |
|
|
plots_tests_plugin_read_systemverilog
|
35.7 KB |
|
|
plots_tests_plugin_read_uhdm
|
33.1 KB |
|
|
plots_tests_release_read_systemverilog
|
34.2 KB |
|
|
plots_tests_release_read_uhdm
|
32 KB |
|
|
plots_veer_synth
|
38.2 KB |
|
|
python_bp_e_bp_unicore_cfg.edif
|
3.92 MB |
|
|
results_parsing_tests_asan_read_systemverilog
Expired
|
1.6 MB |
|
|
results_parsing_tests_asan_read_uhdm
Expired
|
1.81 MB |
|
|
results_parsing_tests_plugin_read_systemverilog
Expired
|
1.53 MB |
|
|
results_parsing_tests_plugin_read_uhdm
Expired
|
1.78 MB |
|
|
results_parsing_tests_release_read_systemverilog
Expired
|
1.48 MB |
|
|
results_parsing_tests_release_read_uhdm
Expired
|
1.73 MB |
|
|
tools
|
39.2 MB |
|
|
top_artya7.bit
|
122 KB |
|