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Update outdated naming (#2686) #6079

Job	Run time
Style check	1m 32s
Build Synlig Release	4m 36s
Build tools	10m 38s
Build Plugin	4m 22s
Build Synlig (ASAN)	10m 9s
Emit Workflow Info	0s
Build Package	5m 1s
Build PySynlig	11m 3s
Verify README Correctness (Installation From Sources)	43m 51s
Large Designs Tests / Opentitan (synthesis)	1h 6m 11s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 10s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	33m 0s
Large Designs Tests / Ibex (Vivado synthesis)	6m 27s
Large Designs Tests / Black Parrot (ASIC synthesis)	41m 46s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	23m 34s
Large Designs Tests / Opentitan parsing (full/top-down)	15m 21s
Large Designs Tests / Opentitan parsing (quick)	6m 21s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 10s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 24s
Formal Verification Tests / simple	15m 21s
Formal Verification Tests / sv2v	15m 3s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	41m 30s
Formal Verification Tests / yosys	12m 57s
Parsing Tests / Test read_systemverilog release	4m 27s
Parsing Tests / Test read_uhdm release	4m 17s
Parsing Tests / Test read_systemverilog plugin	4m 54s
Parsing Tests / Test read_uhdm plugin	4m 21s
Parsing Tests / Test read_systemverilog asan	39m 44s
Parsing Tests / Test read_uhdm asan	25m 13s
Parsing Tests / Summary Generation	1m 18s
Parsing Tests / Generate AST diff	1m 32s
Release Package	11s
Verify README Correctness (Download And Run Release)	1m 47s
	7h 59m 11s

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