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Removing black-parrot-tools and black-parrot-sdk #6064

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Removing black-parrot-tools and black-parrot-sdk

Removing black-parrot-tools and black-parrot-sdk #6064

Re-run triggered November 26, 2024 07:51
@kamilrakoczykamilrakoczy
#2660
dpetrisko:main
Status Failure
Total duration 1h 7m 30s
Artifacts 47

main.yml

on: pull_request
Matrix: build-binaries
Build tools
10m 44s
Build tools
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 32s
Style check
Verify README Correctness (Installation From Sources)
41m 22s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 29s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
12m 27s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
33m 39s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
56m 50s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 16s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
11m 40s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
9m 55s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
34m 23s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 29s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 46s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

3 errors and 3 warnings
Large Designs Tests / Black Parrot (ASIC synthesis)
Process completed with exit code 2.
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Process completed with exit code 2.
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Process completed with exit code 2.
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
291 MB
binaries-package
23.2 MB
binaries-plugin
41.7 MB
binaries-pysynlig
651 MB
binaries-release
41.9 MB
bsg-logs
5.57 MB
bsg-outputs
1.73 MB
formal-verification-logs-simple
18.6 MB
formal-verification-logs-sv2v
62.6 MB
formal-verification-logs-yosys
50.1 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit
105 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
4.58 MB
opentitan-logs-quick
832 KB
plots_binaries-asan
54.1 KB
plots_binaries-package
31.5 KB
plots_binaries-plugin
29.7 KB
plots_binaries-pysynlig
63.7 KB
plots_binaries-release
32.5 KB
plots_blackparrot_synth_asic
64.8 KB
plots_blackparrot_synth_xilinx
73.5 KB
plots_blackparrot_synth_xilinx_python
197 KB
plots_build_tools
77.2 KB
plots_formal_verification_simple
114 KB
plots_formal_verification_sv2v
116 KB
plots_formal_verification_yosys
97.4 KB
plots_ibex_synth
46.2 KB
plots_ibex_synth_f4pga
85.8 KB
plots_opentitan_9d82960888_synth
189 KB
plots_opentitan_parse_report_full
79 KB
plots_opentitan_parse_report_quick
36.6 KB
plots_opentitan_synth
301 KB
plots_tests_asan_read_systemverilog
223 KB
plots_tests_asan_read_uhdm
167 KB
plots_tests_plugin_read_systemverilog
35.7 KB
plots_tests_plugin_read_uhdm
34 KB
plots_tests_release_read_systemverilog
36.3 KB
plots_tests_release_read_uhdm
33 KB
plots_veer_synth
36.8 KB
results_parsing_tests_asan_read_systemverilog Expired
1.6 MB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
1.53 MB
results_parsing_tests_plugin_read_uhdm Expired
1.78 MB
results_parsing_tests_release_read_systemverilog Expired
1.49 MB
results_parsing_tests_release_read_uhdm Expired
1.73 MB
tools
39.2 MB
top_artya7.bit
122 KB