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chipsalliance / synlig Public

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Adjust Synlig to recent Yosys changes (#2668) #6058

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Adjust Synlig to recent Yosys changes (#2668)

Adjust Synlig to recent Yosys changes (#2668) #6058

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Usage Workflow file

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1 warning

No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.

Large Designs Tests / VeeR-EH1 (synthesis)

succeeded Nov 22, 2024 in 5m 26s

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