Adjust Synlig to recent Yosys changes (#2668) #6058
tgorochowikmain.yml
on: push
Matrix: build-binaries
Build tools
10m 47s
Emit Workflow Info
0s
Style check
1m 33s
Verify README Correctness (Installation From Sources)
42m 12s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 25s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 35s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
28m 15s
Large Designs Tests
/
Opentitan (synthesis)
49m 0s
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 26s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
15m 0s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
31m 0s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
31m 16s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 20s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
1m 47s
Parsing Tests
/
Summary Generation
1m 32s
Verify README Correctness (Download And Run Release)
1m 52s
Annotations
1 error and 6 warnings
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Large Designs Tests / Opentitan parsing (quick)
unable to access 'https://github.com/chipsalliance/synlig/': Failed to connect to github.com port 443 after 129548 ms: Operation timed out
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
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Release Package
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/checkout@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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Release Package
The following actions use a deprecated Node.js version and will be forced to run on node20: actions/checkout@v2, 8BitJonny/[email protected]. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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binaries-asan
|
291 MB |
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binaries-package
|
23.2 MB |
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binaries-plugin
|
41.6 MB |
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binaries-pysynlig
|
651 MB |
|
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binaries-release
|
41.9 MB |
|
|
bp_e_bp_unicore_cfg.edif
|
3.92 MB |
|
|
bsg-logs
|
5.57 MB |
|
|
bsg-outputs
|
1.73 MB |
|
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formal-verification-logs-simple
|
18.2 MB |
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|
formal-verification-logs-sv2v
|
62.7 MB |
|
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formal-verification-logs-yosys
|
50 MB |
|
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lowrisc_ibex_top_artya7_surelog_0.1.bit
|
105 KB |
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lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
616 KB |
|
|
opentitan-logs-full
|
5.08 MB |
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|
opentitan-logs-quick
|
1.52 MB |
|
|
opentitan-synlig.ast
|
134 MB |
|
|
plots_binaries-asan
|
147 KB |
|
|
plots_binaries-package
|
140 KB |
|
|
plots_binaries-plugin
|
148 KB |
|
|
plots_binaries-pysynlig
|
175 KB |
|
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plots_binaries-release
|
148 KB |
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plots_blackparrot_synth_asic
|
180 KB |
|
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plots_blackparrot_synth_xilinx
|
97 KB |
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|
plots_blackparrot_synth_xilinx_python
|
181 KB |
|
|
plots_build_tools
|
80.3 KB |
|
|
plots_formal_verification_simple
|
118 KB |
|
|
plots_formal_verification_sv2v
|
100 KB |
|
|
plots_formal_verification_yosys
|
89.7 KB |
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|
plots_ibex_synth
|
45.6 KB |
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plots_ibex_synth_f4pga
|
83 KB |
|
|
plots_opentitan_9d82960888_synth
|
164 KB |
|
|
plots_opentitan_parse_report_full
|
85.4 KB |
|
|
plots_opentitan_parse_report_quick
|
53.5 KB |
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plots_opentitan_synth
|
264 KB |
|
|
plots_tests_asan_read_systemverilog
|
226 KB |
|
|
plots_tests_asan_read_uhdm
|
165 KB |
|
|
plots_tests_plugin_read_systemverilog
|
35.4 KB |
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plots_tests_plugin_read_uhdm
|
33.6 KB |
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plots_tests_release_read_systemverilog
|
35.9 KB |
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plots_tests_release_read_uhdm
|
32.9 KB |
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|
plots_veer_synth
|
37.5 KB |
|
|
python_bp_e_bp_unicore_cfg.edif
|
3.92 MB |
|
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results_parsing_tests_asan_read_systemverilog
Expired
|
1.6 MB |
|
|
results_parsing_tests_asan_read_uhdm
Expired
|
1.81 MB |
|
|
results_parsing_tests_plugin_read_systemverilog
Expired
|
1.53 MB |
|
|
results_parsing_tests_plugin_read_uhdm
Expired
|
1.78 MB |
|
|
results_parsing_tests_release_read_systemverilog
Expired
|
1.49 MB |
|
|
results_parsing_tests_release_read_uhdm
Expired
|
1.73 MB |
|
|
tools
|
39.2 MB |
|
|
top_artya7.bit
|
119 KB |
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