Merge pull request #5139 from sifferman/unsynthesizable

Added `unsynthesizable` test parameter
chipsalliance · Oct 13, 2023 · 40f7b15 · 40f7b15
2 parents b1db937 + 6fa5351
commit 40f7b15
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Showing 340 changed files with 375 additions and 25 deletions.
diff --git a/conf/generators/templates/uvm-classes_0.sv b/conf/generators/templates/uvm-classes_0.sv
@@ -12,6 +12,7 @@
 :description: {0} class test
 :tags: uvm uvm-classes
 :type: simulation elaboration parsing
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;
@@ -23,41 +24,41 @@ class C extends {0};
         super.new(name, parent);
         `uvm_info("RESULT", "new {0} created", UVM_LOW);
     endfunction
-    
+
     virtual function void build_phase(uvm_phase phase);
         super.build_phase(phase);
         `uvm_info("RESULT", "build phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void connect_phase(uvm_phase phase);
         super.connect_phase(phase);
         `uvm_info("RESULT", "connect phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void end_of_elaboration_phase(uvm_phase phase);
         super.end_of_elaboration_phase(phase);
         `uvm_info("RESULT", "end of elaboration phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void start_of_simulation_phase(uvm_phase phase);
         super.start_of_simulation_phase(phase);
         `uvm_info("RESULT", "start of simulation phase completed", UVM_LOW);
     endfunction
-    
+
     task run_phase(uvm_phase phase);
         `uvm_info("RESULT", "run phase phase completed", UVM_LOW);
     endtask
-    
+
     virtual function void extract_phase(uvm_phase phase);
         super.extract_phase(phase);
         `uvm_info("RESULT", "extract phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void check_phase(uvm_phase phase);
         super.check_phase(phase);
         `uvm_info("RESULT", "check phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void report_phase(uvm_phase phase);
         super.report_phase(phase);
         `uvm_info("RESULT", "report phase completed", UVM_LOW);

diff --git a/conf/generators/templates/uvm-classes_1.sv b/conf/generators/templates/uvm-classes_1.sv
@@ -12,6 +12,7 @@
 :description: {0} class test
 :tags: uvm uvm-classes
 :type: simulation elaboration parsing
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;
@@ -37,25 +38,25 @@ endmodule
 class C extends {0};
     virtual output_if out_vif;
     virtual input_if in_vif;
-    
+
     `uvm_component_utils(C)
-    
+
     function new(string name, uvm_component parent = null);
         super.new(name, parent);
     endfunction
-    
+
     virtual function void connect_phase(uvm_phase phase);
         super.connect_phase(phase);
         assert(uvm_resource_db#(virtual input_if)::read_by_name(
             "C", "input_if", in_vif));
         assert(uvm_resource_db#(virtual output_if)::read_by_name(
             "C", "output_if", out_vif));
     endfunction
-    
+
     virtual function void build_phase(uvm_phase phase);
         super.build_phase(phase);
     endfunction
-    
+
     task run_phase(uvm_phase phase);
         phase.raise_objection(this);
         `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW);
@@ -79,9 +80,9 @@ module top;
     input_if in(clk);
     output_if out(clk);
     dut d(in, out);
-    
+
     always #5 clk = !clk;
-    
+
     initial begin
         obj = new("C");
         uvm_resource_db#(virtual input_if)::set("C","input_if", in);

diff --git a/conf/generators/templates/uvm-classes_3.sv b/conf/generators/templates/uvm-classes_3.sv
@@ -12,6 +12,7 @@
 :description: {0} class test
 :tags: uvm uvm-classes
 :type: simulation elaboration parsing
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;
@@ -28,7 +29,7 @@ endclass
 
 module top;
     C obj;
-    
+
     initial begin
         obj = new("C");
     end

diff --git a/generators/easyUVM b/generators/easyUVM
@@ -20,6 +20,7 @@ templ = """/*
 :incdirs: {1}
 :tags: uvm
 :timeout: 100
+:unsynthesizable: 1
 */
 """
 

diff --git a/tests/chapter-11/11.4.14.4--dynamic_array_stream-sim.sv b/tests/chapter-11/11.4.14.4--dynamic_array_stream-sim.sv
@@ -12,6 +12,7 @@
 :description: stream unpack simulation test with dynamic array
 :type: simulation elaboration parsing
 :tags: 11.4.14.4
+:unsynthesizable: 1
 */
 module top();
 

diff --git a/tests/chapter-11/11.4.14.4--dynamic_array_stream.sv b/tests/chapter-11/11.4.14.4--dynamic_array_stream.sv
@@ -11,6 +11,7 @@
 :name: dynamic_array_unpack_stream
 :description: stream unpack test with dynamic array
 :tags: 11.4.14.4
+:unsynthesizable: 1
 */
 module top();
 

diff --git a/tests/chapter-11/11.4.14.4--dynamic_array_stream_with.sv b/tests/chapter-11/11.4.14.4--dynamic_array_stream_with.sv
@@ -11,6 +11,7 @@
 :name: dynamic_array_unpack_stream_with
 :description: stream unpack test with dynamic array using with
 :tags: 11.4.14.4
+:unsynthesizable: 1
 */
 module top();
 

diff --git a/tests/chapter-12/12.7.3--foreach.sv b/tests/chapter-12/12.7.3--foreach.sv
@@ -11,6 +11,7 @@
 :name: foreach_loop
 :description: A module testing foreach loop
 :tags: 12.7.3
+:unsynthesizable: 1
 */
 module foreach_tb ();
 	string test [4] = '{"111", "222", "333", "444"};

diff --git a/tests/chapter-12/12.7.6--forever.sv b/tests/chapter-12/12.7.6--forever.sv
@@ -11,8 +11,9 @@
 :name: forever_loop
 :description: A module testing forever loop
 :tags: 12.7.6
+:unsynthesizable: 1
 */
-module foreach_tb ();
+module forever_tb ();
    initial begin
       forever begin : loop
 	 disable loop;

diff --git a/tests/chapter-13/13.3.1--task-static.sv b/tests/chapter-13/13.3.1--task-static.sv
@@ -12,6 +12,7 @@
 :description: static task test
 :tags: 13.3.1
 :type: simulation elaboration parsing
+:unsynthesizable: 1
 */
 module top();
 

diff --git a/tests/chapter-13/13.4.2--function-static.sv b/tests/chapter-13/13.4.2--function-static.sv
@@ -11,6 +11,7 @@
 :name: function_static
 :description: static function test
 :tags: 13.4.2
+:unsynthesizable: 1
 */
 module top();
 

diff --git a/tests/chapter-13/13.4.4--fork-invalid.sv b/tests/chapter-13/13.4.4--fork-invalid.sv
@@ -13,6 +13,7 @@
 :should_fail_because: only fork-join_none is permitted inside a function
 :tags: 13.4.4
 :type: simulation elaboration
+:unsynthesizable: 1
 */
 module top();
 

diff --git a/tests/chapter-13/13.4.4--fork-valid.sv b/tests/chapter-13/13.4.4--fork-valid.sv
@@ -12,6 +12,7 @@
 :description: function valid fork test
 :tags: 13.4.4
 :type: simulation elaboration parsing
+:unsynthesizable: 1
 */
 module top();
 

diff --git a/tests/chapter-14/14.3--clocking-block-signals-error.sv b/tests/chapter-14/14.3--clocking-block-signals-error.sv
@@ -13,6 +13,7 @@
 :should_fail_because: assigning to net from procedural context
 :type: simulation elaboration
 :tags: 14.3
+:unsynthesizable: 1
 */
 module top(input clk, input a, output b, output c);
 

diff --git a/tests/chapter-14/14.3--clocking-block-signals.sv b/tests/chapter-14/14.3--clocking-block-signals.sv
@@ -11,6 +11,7 @@
 :name: clocking_block_signals
 :description: clocking block with signals test
 :tags: 14.3
+:unsynthesizable: 1
 */
 module top(input clk, input a, output logic b, output logic c);
 

diff --git a/tests/chapter-14/14.3--clocking-block.sv b/tests/chapter-14/14.3--clocking-block.sv
@@ -11,6 +11,7 @@
 :name: clocking_block
 :description: clocking block test
 :tags: 14.3
+:unsynthesizable: 1
 */
 module top(input clk);
 

diff --git a/tests/chapter-14/14.3--default-clocking-block.sv b/tests/chapter-14/14.3--default-clocking-block.sv
@@ -11,6 +11,7 @@
 :name: default_clocking_block
 :description: default clocking block test
 :tags: 14.3
+:unsynthesizable: 1
 */
 module top(input clk);
 

diff --git a/tests/chapter-14/14.3--global-clocking-block.sv b/tests/chapter-14/14.3--global-clocking-block.sv
@@ -11,6 +11,7 @@
 :name: global_clocking_block
 :description: global clocking block test
 :tags: 14.3
+:unsynthesizable: 1
 */
 module top(input clk);
 

diff --git a/tests/chapter-15/15.5.1--named-event-trigger-blocking.sv b/tests/chapter-15/15.5.1--named-event-trigger-blocking.sv
@@ -12,6 +12,7 @@
 :description: Trigger named event, blocking
 :tags: 15.5
 :top_module: top
+:unsynthesizable: 1
 */
 
 

diff --git a/tests/chapter-15/15.5.1--named-event-trigger-non-blocking.sv b/tests/chapter-15/15.5.1--named-event-trigger-non-blocking.sv
@@ -12,6 +12,7 @@
 :description: Trigger named event, non-blocking
 :tags: 15.5
 :top_module: top
+:unsynthesizable: 1
 */
 
 

diff --git a/tests/chapter-15/15.5.2--named-event-wait.sv b/tests/chapter-15/15.5.2--named-event-wait.sv
@@ -12,6 +12,7 @@
 :description: Wait for a named event
 :tags: 15.5
 :top_module: top
+:unsynthesizable: 1
 */
 
 

diff --git a/tests/chapter-16/16.10--property-local-var-fail.sv b/tests/chapter-16/16.10--property-local-var-fail.sv
@@ -13,6 +13,7 @@
 :should_fail_because: pipeline increments value by 4 but property expects incrementation by 3
 :type: simulation
 :tags: 16.10
+:unsynthesizable: 1
 */
 
 module clk_gen(

diff --git a/tests/chapter-16/16.10--property-local-var-uvm-fail.sv b/tests/chapter-16/16.10--property-local-var-uvm-fail.sv
@@ -13,6 +13,7 @@
 :should_fail_because: pipeline increments value by 4 but property expects incrementation by 3
 :type: simulation
 :tags: uvm uvm-assertions
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.10--property-local-var-uvm.sv b/tests/chapter-16/16.10--property-local-var-uvm.sv
@@ -13,6 +13,7 @@
 :type: simulation elaboration parsing
 :tags: uvm uvm-assertions
 :timeout: 60
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.10--property-local-var.sv b/tests/chapter-16/16.10--property-local-var.sv
@@ -12,6 +12,7 @@
 :description: property with local variables
 :type: simulation elaboration parsing
 :tags: 16.10
+:unsynthesizable: 1
 */
 
 module clk_gen(

diff --git a/tests/chapter-16/16.10--sequence-local-var-fail.sv b/tests/chapter-16/16.10--sequence-local-var-fail.sv
@@ -13,6 +13,7 @@
 :should_fail_because: pipeline increments value by 4 but sequence expects incrementation by 3
 :type: simulation
 :tags: 16.10
+:unsynthesizable: 1
 */
 
 module clk_gen(

diff --git a/tests/chapter-16/16.10--sequence-local-var-uvm.sv b/tests/chapter-16/16.10--sequence-local-var-uvm.sv
@@ -13,6 +13,7 @@
 :type: simulation elaboration parsing
 :tags: uvm uvm-assertions
 :timeout: 60
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.10--sequence-local-var.sv b/tests/chapter-16/16.10--sequence-local-var.sv
@@ -12,6 +12,7 @@
 :description: sequence with local variables
 :type: simulation elaboration parsing
 :tags: 16.10
+:unsynthesizable: 1
 */
 
 module clk_gen(

diff --git a/tests/chapter-16/16.11--sequence-subroutine-uvm.sv b/tests/chapter-16/16.11--sequence-subroutine-uvm.sv
@@ -13,6 +13,7 @@
 :type: simulation elaboration parsing
 :tags: uvm uvm-assertions
 :timeout: 60
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.12--property-interface-prec-uvm.sv b/tests/chapter-16/16.12--property-interface-prec-uvm.sv
@@ -13,6 +13,7 @@
 :type: simulation elaboration parsing
 :tags: uvm uvm-assertions
 :timeout: 60
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.12--property-interface-uvm-fail.sv b/tests/chapter-16/16.12--property-interface-uvm-fail.sv
@@ -13,6 +13,7 @@
 :should_fail_because: mem_ctrl asserts read and write at the same time and property checks that one or the other is asserted
 :type: simulation
 :tags: uvm uvm-assertions
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.12--property-interface-uvm.sv b/tests/chapter-16/16.12--property-interface-uvm.sv
@@ -13,6 +13,7 @@
 :type: simulation elaboration parsing
 :tags: uvm uvm-assertions
 :timeout: 60
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.12--property-prec-uvm-fail.sv b/tests/chapter-16/16.12--property-prec-uvm-fail.sv
@@ -13,6 +13,7 @@
 :should_fail_because: mem_ctrl interleaves reads and writes and property requires to keep reading
 :type: simulation
 :tags: uvm uvm-assertions
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.12--property-prec-uvm.sv b/tests/chapter-16/16.12--property-prec-uvm.sv
@@ -13,6 +13,7 @@
 :type: simulation elaboration parsing
 :tags: uvm uvm-assertions
 :timeout: 60
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.12--property-uvm-fail.sv b/tests/chapter-16/16.12--property-uvm-fail.sv
@@ -13,6 +13,7 @@
 :should_fail_because: mem_ctrl asserts read and write at the same time and property checks that one or the other is asserted
 :type: simulation
 :tags: uvm uvm-assertions
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;

diff --git a/tests/chapter-16/16.12--property-uvm.sv b/tests/chapter-16/16.12--property-uvm.sv
@@ -13,6 +13,7 @@
 :type: simulation elaboration parsing
 :tags: uvm uvm-assertions
 :timeout: 60
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;