unsynthesizable uvm generators

chipsalliance · Oct 12, 2023 · 6fa5351 · 6fa5351
1 parent 01d805b
commit 6fa5351
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Showing 4 changed files with 20 additions and 16 deletions.
diff --git a/conf/generators/templates/uvm-classes_0.sv b/conf/generators/templates/uvm-classes_0.sv
@@ -12,6 +12,7 @@
 :description: {0} class test
 :tags: uvm uvm-classes
 :type: simulation elaboration parsing
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;
@@ -23,41 +24,41 @@ class C extends {0};
         super.new(name, parent);
         `uvm_info("RESULT", "new {0} created", UVM_LOW);
     endfunction
-    
+
     virtual function void build_phase(uvm_phase phase);
         super.build_phase(phase);
         `uvm_info("RESULT", "build phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void connect_phase(uvm_phase phase);
         super.connect_phase(phase);
         `uvm_info("RESULT", "connect phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void end_of_elaboration_phase(uvm_phase phase);
         super.end_of_elaboration_phase(phase);
         `uvm_info("RESULT", "end of elaboration phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void start_of_simulation_phase(uvm_phase phase);
         super.start_of_simulation_phase(phase);
         `uvm_info("RESULT", "start of simulation phase completed", UVM_LOW);
     endfunction
-    
+
     task run_phase(uvm_phase phase);
         `uvm_info("RESULT", "run phase phase completed", UVM_LOW);
     endtask
-    
+
     virtual function void extract_phase(uvm_phase phase);
         super.extract_phase(phase);
         `uvm_info("RESULT", "extract phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void check_phase(uvm_phase phase);
         super.check_phase(phase);
         `uvm_info("RESULT", "check phase completed", UVM_LOW);
     endfunction
-    
+
     virtual function void report_phase(uvm_phase phase);
         super.report_phase(phase);
         `uvm_info("RESULT", "report phase completed", UVM_LOW);

diff --git a/conf/generators/templates/uvm-classes_1.sv b/conf/generators/templates/uvm-classes_1.sv
@@ -12,6 +12,7 @@
 :description: {0} class test
 :tags: uvm uvm-classes
 :type: simulation elaboration parsing
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;
@@ -37,25 +38,25 @@ endmodule
 class C extends {0};
     virtual output_if out_vif;
     virtual input_if in_vif;
-    
+
     `uvm_component_utils(C)
-    
+
     function new(string name, uvm_component parent = null);
         super.new(name, parent);
     endfunction
-    
+
     virtual function void connect_phase(uvm_phase phase);
         super.connect_phase(phase);
         assert(uvm_resource_db#(virtual input_if)::read_by_name(
             "C", "input_if", in_vif));
         assert(uvm_resource_db#(virtual output_if)::read_by_name(
             "C", "output_if", out_vif));
     endfunction
-    
+
     virtual function void build_phase(uvm_phase phase);
         super.build_phase(phase);
     endfunction
-    
+
     task run_phase(uvm_phase phase);
         phase.raise_objection(this);
         `uvm_info("RESULT", $sformatf("Writing %0d to input interface", `PATTERN), UVM_LOW);
@@ -79,9 +80,9 @@ module top;
     input_if in(clk);
     output_if out(clk);
     dut d(in, out);
-    
+
     always #5 clk = !clk;
-    
+
     initial begin
         obj = new("C");
         uvm_resource_db#(virtual input_if)::set("C","input_if", in);

diff --git a/conf/generators/templates/uvm-classes_3.sv b/conf/generators/templates/uvm-classes_3.sv
@@ -12,6 +12,7 @@
 :description: {0} class test
 :tags: uvm uvm-classes
 :type: simulation elaboration parsing
+:unsynthesizable: 1
 */
 
 import uvm_pkg::*;
@@ -28,7 +29,7 @@ endclass
 
 module top;
     C obj;
-    
+
     initial begin
         obj = new("C");
     end

diff --git a/generators/easyUVM b/generators/easyUVM
@@ -20,6 +20,7 @@ templ = """/*
 :incdirs: {1}
 :tags: uvm
 :timeout: 100
+:unsynthesizable: 1
 */
 """