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Update SRAM.scala to improve perf on non-full sized reads #3614

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Apr 15, 2024
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9 changes: 5 additions & 4 deletions src/main/scala/tilelink/SRAM.scala
Original file line number Diff line number Diff line change
Expand Up @@ -229,14 +229,15 @@ class TLRAM(
val r_ready = !d_wb && !r_replay && (!d_full || d_ready) && (!r_respond || (!d_win && in.d.ready))
in.a.ready := !(d_full && d_wb) && (!r_full || r_ready) && (!r_full || !(r_atomic || r_sublane))

// ignore sublane if mask is all set
// ignore sublane if it is a read or mask is all set
val a_read = in.a.bits.opcode === TLMessages.Get
val a_sublane = if (eccBytes == 1) false.B else
((in.a.bits.opcode === TLMessages.PutPartialData) && (~in.a.bits.mask.andR)) ||
in.a.bits.size < log2Ceil(eccBytes).U
~a_read &&
(((in.a.bits.opcode === TLMessages.PutPartialData) && (~in.a.bits.mask.andR)) ||
in.a.bits.size < log2Ceil(eccBytes).U)
val a_atomic = if (!atomics) false.B else
in.a.bits.opcode === TLMessages.ArithmeticData ||
in.a.bits.opcode === TLMessages.LogicalData
val a_read = in.a.bits.opcode === TLMessages.Get

// Forward pipeline stage from R to D
when (d_ready) { d_full := false.B }
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