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Add a generator which works with Yosys
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Yosys can't handle automatic logic within always blocks
leviathanch authored and David Lanzendörfer committed Aug 21, 2024
1 parent c8d8e0c commit 9791a5e
Showing 1 changed file with 29 additions and 0 deletions.
29 changes: 29 additions & 0 deletions build.sc
Original file line number Diff line number Diff line change
@@ -136,6 +136,35 @@ trait Emulator extends Cross.Module2[String, String] {
}
}

object litexgenerate extends Module {
def compile = T {
os.proc("firtool",
generator.chirrtl().path,
s"--annotation-file=${generator.chiselAnno().path}",
"--disable-annotation-unknown",
"-dedup",
"-O=debug",
"--split-verilog",
"--preserve-values=named",
"--output-annotation-file=mfc.anno.json",
"--lowering-options=disallowLocalVariables",
s"-o=${T.dest}"
).call(T.dest)
PathRef(T.dest)
}

def rtls = T {
os.read(compile().path / "filelist.f").split("\n").map(str =>
try {
os.Path(str)
} catch {
case e: IllegalArgumentException if e.getMessage.contains("is not an absolute path") =>
compile().path / str.stripPrefix("./")
}
).filter(p => p.ext == "v" || p.ext == "sv").map(PathRef(_)).toSeq
}
}

object mfccompiler extends Module {
def compile = T {
os.proc("firtool",

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