Adding support for Litex

There is a naming conflict of the ALU module which prevents a
successful synthesis with Yosys. This patch fixes this conflict.

In addition, this patch introduces the configurations expected
by Litex when generating an SoC

build.sc

@@ -184,7 +184,7 @@ trait Emulator extends Cross.Module2[String, String] {
         "debug_rob.cc",
         "emulator.cc",
         "remote_bitbang.cc",
-        ).map(c => PathRef(csrcDir().path / c))
+      ).map(c => PathRef(csrcDir().path / c))
     }
 
     def CMakeListsString = T {
@@ -294,6 +294,41 @@ object emulator extends Cross[Emulator](
   //
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"),
+  // Litex
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x1"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x2"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x4"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall1x8"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x1"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x2"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x4"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall2x8"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x1"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x2"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x4"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall4x8"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x1"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x2"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x4"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigSmall8x8"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x1"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x2"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x4"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig1x8"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x1"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x2"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x4"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig2x8"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x1"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x2"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x4"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig4x8"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x1"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x2"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x4"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.LitexConfigBig8x8"),
 )
 
 object `runnable-riscv-test` extends mill.Cross[RiscvTest](

src/main/scala/rocket/ALU.scala

@@ -65,6 +65,8 @@ abstract class AbstractALU[T <: ALUFN](val aluFn: T)(implicit p: Parameters) ext
 }
 
 class ALU(implicit p: Parameters) extends AbstractALU(new ALUFN)(p) {
+  override def desiredName = "RocketALU"
+
   // ADD, SUB
   val in2_inv = Mux(aluFn.isSub(io.fn), ~io.in2, io.in2)
   val in1_xor_in2 = io.in1 ^ in2_inv

src/main/scala/subsystem/Litex.scala

@@ -0,0 +1,40 @@
+// See LICENSE.SiFive for license details.
+// See LICENSE.Berkeley for license details.
+
+package freechips.rocketchip.subsystem
+
+import chisel3.util._
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.rocket._
+import freechips.rocketchip.tile._
+import freechips.rocketchip.util._
+
+class WithLitexMemPort extends Config((site, here, up) => {
+  case ExtMem => Some(MemoryPortParams(MasterPortParams(
+                      base = x"8000_0000",
+                      size = x"8000_0000",
+                      beatBytes = site(MemoryBusKey).beatBytes,
+                      idBits = 4), 1))
+})
+
+class WithLitexMMIOPort extends Config((site, here, up) => {
+  case ExtBus => Some(MasterPortParams(
+                      base = x"1000_0000",
+                      size = x"7000_0000",
+                      beatBytes = site(SystemBusKey).beatBytes,
+                      idBits = 4))
+})
+
+class WithLitexSlavePort extends Config((site, here, up) => {
+  case ExtIn  => Some(SlavePortParams(
+                      beatBytes = site(SystemBusKey).beatBytes,
+                      idBits = 8,
+                      sourceBits = 4))
+})
+
+class WithNBitMemoryBus(dataBits: Int) extends Config((site, here, up) => {
+  case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
+})

src/main/scala/system/Litex.scala

@@ -0,0 +1,208 @@
+// See LICENSE.SiFive for license details.
+// See LICENSE.Berkeley for license details.
+
+package freechips.rocketchip.system
+
+import org.chipsalliance.cde.config.Config
+import freechips.rocketchip.subsystem._
+
+class BaseLitexConfig extends Config(
+  new WithLitexMemPort() ++
+  new WithLitexMMIOPort() ++
+  new WithLitexSlavePort ++
+  new WithNExtTopInterrupts(8) ++
+  new WithCoherentBusTopology ++
+  new BaseConfig
+)
+
+class LitexConfigSmall1x1 extends Config(
+  new WithNSmallCores(1) ++
+  new WithNBitMemoryBus(64) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall1x2 extends Config(
+  new WithNSmallCores(1) ++
+  new WithNBitMemoryBus(128) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall1x4 extends Config(
+  new WithNSmallCores(1) ++
+  new WithNBitMemoryBus(256) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall1x8 extends Config(
+  new WithNSmallCores(1) ++
+  new WithNBitMemoryBus(512) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall2x1 extends Config(
+  new WithNSmallCores(2) ++
+  new WithNBitMemoryBus(64) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall2x2 extends Config(
+  new WithNSmallCores(2) ++
+  new WithNBitMemoryBus(128) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall2x4 extends Config(
+  new WithNSmallCores(2) ++
+  new WithNBitMemoryBus(256) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall2x8 extends Config(
+  new WithNSmallCores(2) ++
+  new WithNBitMemoryBus(512) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall4x1 extends Config(
+  new WithNSmallCores(4) ++
+  new WithNBitMemoryBus(64) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall4x2 extends Config(
+  new WithNSmallCores(4) ++
+  new WithNBitMemoryBus(128) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall4x4 extends Config(
+  new WithNSmallCores(4) ++
+  new WithNBitMemoryBus(256) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall4x8 extends Config(
+  new WithNSmallCores(4) ++
+  new WithNBitMemoryBus(512) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall8x1 extends Config(
+  new WithNSmallCores(8) ++
+  new WithNBitMemoryBus(64) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall8x2 extends Config(
+  new WithNSmallCores(8) ++
+  new WithNBitMemoryBus(128) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall8x4 extends Config(
+  new WithNSmallCores(8) ++
+  new WithNBitMemoryBus(256) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigSmall8x8 extends Config(
+  new WithNSmallCores(8) ++
+  new WithNBitMemoryBus(512) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig1x1 extends Config(
+  new WithNBigCores(1) ++
+  new WithNBitMemoryBus(64) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig1x2 extends Config(
+  new WithNBigCores(1) ++
+  new WithNBitMemoryBus(128) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig1x4 extends Config(
+  new WithNBigCores(1) ++
+  new WithNBitMemoryBus(256) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig1x8 extends Config(
+  new WithNBigCores(1) ++
+  new WithNBitMemoryBus(512) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig2x1 extends Config(
+  new WithNBigCores(2) ++
+  new WithNBitMemoryBus(64) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig2x2 extends Config(
+  new WithNBigCores(2) ++
+  new WithNBitMemoryBus(128) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig2x4 extends Config(
+  new WithNBigCores(2) ++
+  new WithNBitMemoryBus(256) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig2x8 extends Config(
+  new WithNBigCores(2) ++
+  new WithNBitMemoryBus(512) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig4x1 extends Config(
+  new WithNBigCores(4) ++
+  new WithNBitMemoryBus(64) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig4x2 extends Config(
+  new WithNBigCores(4) ++
+  new WithNBitMemoryBus(128) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig4x4 extends Config(
+  new WithNBigCores(4) ++
+  new WithNBitMemoryBus(256) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig4x8 extends Config(
+  new WithNBigCores(4) ++
+  new WithNBitMemoryBus(512) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig8x1 extends Config(
+  new WithNBigCores(8) ++
+  new WithNBitMemoryBus(64) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig8x2 extends Config(
+  new WithNBigCores(8) ++
+  new WithNBitMemoryBus(128) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig8x4 extends Config(
+  new WithNBigCores(8) ++
+  new WithNBitMemoryBus(256) ++
+  new BaseLitexConfig
+)
+
+class LitexConfigBig8x8 extends Config(
+  new WithNBigCores(8) ++
+  new WithNBitMemoryBus(512) ++
+  new BaseLitexConfig
+)