add test for FlatIO port ordering #4113
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mwachs5
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mwachs5
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mwachs5
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jackkoenig
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| matchesAndOmits( | ||
| ChiselStage.emitSystemVerilog(new MyModule) | ||
| )("io_foo,")("io_bar,") | ||
|
|
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| matchesAndOmits( | ||
| ChiselStage.emitSystemVerilog(new MyFlatIOModule) | ||
| )("foo,")("bar,") | ||
| } |
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Clever, I need to just finish and merge #3410 as that would be a good way to test this.
I wonder if we should also check Vec and also check recursive order...
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(cherry picked from commit c3c9979) # Conflicts: # src/test/scala/chiselTests/experimental/FlatIOSpec.scala
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(cherry picked from commit c3c9979)
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* Add test for FlatIO port ordering (#4113) (cherry picked from commit c3c9979) # Conflicts: # src/test/scala/chiselTests/experimental/FlatIOSpec.scala * Added MatchesOrOmits * Resolve backport conflicts --------- Co-authored-by: Megan Wachs <[email protected]> Co-authored-by: Adam Izraelevitz <[email protected]> Co-authored-by: Jack Koenig <[email protected]>
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(cherry picked from commit c3c9979) Co-authored-by: Megan Wachs <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This is just a unit test. I thought going into writing the test that FlatIO maybe was not working as we intended, but i think it is just general misunderstanding of how Record and Bundle treat their elements.
This might be more of a test of CIRCT's lowering ABI, but firtool internally considers the port order part of the contract (not just the name of the signals), so check that we are doing what is sane here.
Contributor Checklist
docs/src?Type of Improvement
Desired Merge Strategy
Release Notes
Added a unit test for FlatIO Ordering being maintained
Reviewer Checklist (only modified by reviewer)
3.6.x,5.x, or6.xdepending on impact, API modification or big change:7.0)?Enable auto-merge (squash), clean up the commit message, and label withPlease Merge.Create a merge commit.