Add test for FlatIO port ordering (#4113)

(cherry picked from commit c3c9979)

# Conflicts:
#	src/test/scala/chiselTests/experimental/FlatIOSpec.scala

src/test/scala/chiselTests/experimental/FlatIOSpec.scala

@@ -5,10 +5,18 @@ package chiselTests.experimental
 import chisel3._
 import chisel3.util.Valid
 import circt.stage.ChiselStage.emitCHIRRTL
+<<<<<<< HEAD
 import chisel3.experimental.{Analog, FlatIO}
 import chiselTests.ChiselFlatSpec
+=======
+import chisel3.experimental.Analog
+import chiselTests.{ChiselFlatSpec, MatchesAndOmits}
+import chisel3.reflect.DataMirror
+import scala.collection.immutable.SeqMap
+import circt.stage.ChiselStage
+>>>>>>> c3c997939 (Add test for FlatIO port ordering (#4113))
 
-class FlatIOSpec extends ChiselFlatSpec {
+class FlatIOSpec extends ChiselFlatSpec with MatchesAndOmits {
   behavior.of("FlatIO")
 
   it should "create ports without a prefix" in {
@@ -36,7 +44,7 @@ class FlatIOSpec extends ChiselFlatSpec {
     chirrtl should include("out.valid <= valid")
   }
 
-  it should "dynamically indexing Vecs inside of FlatIOs" in {
+  it should "support dynamically indexing Vecs inside of FlatIOs" in {
     class MyModule extends RawModule {
       val io = FlatIO(new Bundle {
         val addr = Input(UInt(2.W))
@@ -65,4 +73,58 @@ class FlatIOSpec extends ChiselFlatSpec {
     chirrtl should include("out.foo <= in.foo")
     chirrtl should include("attach (out.bar, in.bar)")
   }
+<<<<<<< HEAD
+=======
+
+  it should "be an `IO` for elements and vectors" in {
+
+    class Foo extends RawModule {
+      val a = FlatIO(UInt(1.W))
+      val b = FlatIO(Vec(2, UInt(2.W)))
+    }
+    val chirrtl = emitCHIRRTL(new Foo)
+    chirrtl should include("output a : UInt<1>")
+    chirrtl should include("output b : UInt<2>[2]")
+  }
+
+  it should "maintain port order for Bundles" in {
+    class MyBundle extends Bundle {
+      val foo = Bool()
+      val bar = Bool()
+    }
+    class MyModule extends Module {
+      val io = IO(Input(new MyBundle))
+    }
+    class MyFlatIOModule extends Module {
+      val io = FlatIO(Input(new MyBundle))
+    }
+
+    matchesAndOmits(
+      ChiselStage.emitSystemVerilog(new MyModule)
+    )("io_foo,")("io_bar,")
+
+    matchesAndOmits(
+      ChiselStage.emitSystemVerilog(new MyFlatIOModule)
+    )("foo,")("bar,")
+  }
+
+  it should "maintain port order for Records" in {
+    class MyRecord extends Record {
+      val elements = SeqMap("foo" -> Bool(), "bar" -> Bool())
+    }
+    class MyModule extends Module {
+      val io = IO(Input(new MyRecord))
+    }
+    class MyFlatIOModule extends Module {
+      val io = FlatIO(Input(new MyRecord))
+    }
+    matchesAndOmits(
+      ChiselStage.emitSystemVerilog(new MyModule)
+    )("io_bar,")("io_foo,")
+    matchesAndOmits(
+      ChiselStage.emitSystemVerilog(new MyFlatIOModule)
+    )("bar,")("foo,")
+  }
+
+>>>>>>> c3c997939 (Add test for FlatIO port ordering (#4113))
 }