Integrate main-next

[mkurc-ant]

This PR intends to merge recent changes from main-next to main. These include:

• Possibility for injecting custom modules for clock gates (Replacing hand instantiated clock gate cells #50, Add a way of injecting user module for clock gate(s) #54)
• Correction of default WIDTH parameter for rvdffppe (rvdffppe elab issue #73, Correction of default WIDTH param value of rvdffppe #76)
• Fix for swapped mnemonics (srai srli opcode swap in SweRV #42, Fix swapped mnemonics #77)
• Use of RISC-V DV flow for core verification in CI (Use RISC-V DV for core verification #79, Add Renode test case to RISC-V DV CI #82)

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Suggested change

	module el2_pic_ctrl
	import el2_pkg::*;
	module el2_pic_ctrlmodule el2_pic_ctrl
	import el2_pkg::*;

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Declared module does not match the first dot-delimited component of file name: "el2_lib" [Style: file-names] [module-filename]

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 137 [Style: line-length] [line-length]

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 127 [Style: line-length] [line-length]

[github-actions]

⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Suggested change

	module el2_dma_ctrl
	import el2_pkg::*;
	module el2_dma_ctrlmodule el2_dma_ctrl
	import el2_pkg::*;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	endmodule // el2_dec_tlu_ctl
	endmodule // el2_dec_tlu_ctl

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	import el2_pkg::*;
	import el2_pkg::*;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	module el2_dma_ctrl
	import el2_pkg::*;
	module el2_dma_ctrl
	import el2_pkg::*;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	module el2_pic_ctrl
	import el2_pkg::*;
	module el2_pic_ctrl
	import el2_pkg::*;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	assign ifu_fetch_data_f[31:0] = ic_data_f[31:0];
	assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0];
	assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
	logic [1:0] ic_fetch_val_f;
	logic [31:0] ic_data_f;
	logic [31:0] ifu_fetch_data_f;
	logic ifc_fetch_req_f;
	logic ifc_fetch_req_f_raw;
	logic [1:0] iccm_rd_ecc_double_err; // This fetch has an iccm double error.

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	import el2_pkg::*;
	import el2_pkg::*;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	import el2_pkg::*;
	import el2_pkg::*;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic gate;
	logic gate;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	initial gate = 0;
	always @(negedge CK)
	gate <= EN;
	initial gate = 0;
	always @(negedge CK) gate <= EN;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	assign Q = CK & gate;
	assign Q = CK & gate;