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Fix AXI4 to AHB converter issues #141

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merged 6 commits into from
Dec 12, 2023
Merged

Fix AXI4 to AHB converter issues #141

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4e8a3e2
Separate wait state for read and write, untangle R and B AXI channels
mkurc-ant Nov 24, 2023
52c2f77
Remove dependency of AXI valid on AXI ready
mkurc-ant Nov 24, 2023
71a07ed
Update axi4_to_ahb module tests
mkurc-ant Nov 24, 2023
6dbaf82
Fix testbench to work with AHB, VeeR config options as Makefile param…
mkurc-ant Nov 24, 2023
9d5bcad
Add running regression tests for VeeR with AHB to the CI
mkurc-ant Nov 27, 2023
7b1e946
Remove unnecessary AND operation.
mkurc-ant Nov 28, 2023
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25 changes: 19 additions & 6 deletions .github/scripts/run_regression_test.sh
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,25 +7,37 @@ run_regression_test(){
# Run a regression test with coverage collection enabled
# Args:
# RESULTS_DIR -
# BUS -
# NAME -
# COVERAGE -
check_args_count $# 3
check_args_count $# 4
RESULTS_DIR=$1
NAME=$2
COVERAGE=$3
BUS=$2
NAME=$3
COVERAGE=$4
echo -e "${COLOR_WHITE}========== running test '${NAME}' =========${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} RESULTS_DIR = ${RESULTS_DIR}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} SYSTEM BUS = ${BUS}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} NAME = ${NAME}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} COVERAGE = ${COVERAGE}${COLOR_CLEAR}"

if [[ "${BUS}" == "axi" ]]; then
PARAMS="-set build_axi4"
elif [[ "${BUS}" == "ahb" ]]; then
PARAMS="-set build_ahb_lite"
else
echo -e "${COLOR_RED}Unknown system bus type '${BUS}'${COLOR_CLEAR}"
exit 1
fi

mkdir -p ${RESULTS_DIR}
LOG="${RESULTS_DIR}/test_${NAME}_${COVERAGE}.log"
touch ${LOG}
DIR="run_${NAME}_${COVERAGE}"

# Run the test
mkdir -p ${DIR}
make -j`nproc` -C ${DIR} -f $RV_ROOT/tools/Makefile verilator TEST=${NAME} COVERAGE=${COVERAGE} 2>&1 | tee ${LOG}
make -j`nproc` -C ${DIR} -f $RV_ROOT/tools/Makefile verilator CONF_PARAMS="${PARAMS}" TEST=${NAME} COVERAGE=${COVERAGE} 2>&1 | tee ${LOG}
if [ ! -f "${DIR}/coverage.dat" ]; then
echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_RED}FAILED${COLOR_CLEAR}"
exit 1
Expand All @@ -38,11 +50,12 @@ run_regression_test(){

# Example usage
# RESULTS_DIR=results
# BUS=axi
# NAME=hello_world
# COVERAGE=branch
# run_regression_test.sh $RESULTS_DIR $NAME $COVERAGE
# run_regression_test.sh $RESULTS_DIR $BUS $NAME $COVERAGE

check_args_count $# 3
check_args_count $# 4
run_regression_test "$@"


Expand Down
5 changes: 3 additions & 2 deletions .github/workflows/test-regression.yml
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ jobs:
runs-on: ubuntu-latest
strategy:
matrix:
bus: ["axi", "ahb"]
test: ["hello_world", "hello_world_dccm", "hello_world_iccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "pmp"]
coverage: ["branch", "toggle"] #TODO: add functional coverage
env:
Expand Down Expand Up @@ -82,15 +83,15 @@ jobs:
run: |
export PATH=/opt/verilator/bin:$PATH
export RV_ROOT=`pwd`
.github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.test}} ${{ matrix.coverage }}
.github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }}

- name: Prepare coverage data
run: |
.github/scripts/convert_coverage_data.sh ${TEST_PATH}/
echo "convert_coverage_data.sh exited with RET_CODE = "$?
mkdir -p results
mv ${TEST_PATH}/coverage.info \
results/coverage_${{ matrix.test }}_${{ matrix.coverage }}.info
results/coverage_${{ matrix.bus }}_${{ matrix.test }}_${{ matrix.coverage }}.info

- name: Pack artifacts
if: always()
Expand Down
45 changes: 32 additions & 13 deletions design/lib/axi4_to_ahb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -86,13 +86,23 @@

);

localparam ID = 1;

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Raw Output:
design/lib/axi4_to_ahb.sv:89:-   localparam ID   = 1;
design/lib/axi4_to_ahb.sv:90:-   localparam PRTY = 1;
design/lib/axi4_to_ahb.sv:91:-   typedef enum logic [3:0] {
design/lib/axi4_to_ahb.sv:92:-        IDLE            = 4'b0000,
design/lib/axi4_to_ahb.sv:93:-        CMD_RD          = 4'b0001,
design/lib/axi4_to_ahb.sv:94:-        CMD_WR          = 4'b1001,
design/lib/axi4_to_ahb.sv:95:-        DATA_RD         = 4'b0010,
design/lib/axi4_to_ahb.sv:96:-        DATA_WR         = 4'b1010,
design/lib/axi4_to_ahb.sv:97:-        DONE_RD         = 4'b0011,
design/lib/axi4_to_ahb.sv:98:-        DONE_WR         = 4'b1011,
design/lib/axi4_to_ahb.sv:99:-        STREAM_RD       = 4'b0101,
design/lib/axi4_to_ahb.sv:100:-        STREAM_ERR_RD   = 4'b0110
design/lib/axi4_to_ahb.sv:101:-    } state_t;
design/lib/axi4_to_ahb.sv:102:-
design/lib/axi4_to_ahb.sv:103:-   state_t buf_state, buf_nxtstate;
design/lib/axi4_to_ahb.sv:104:-
design/lib/axi4_to_ahb.sv:105:-   logic             slave_valid;
design/lib/axi4_to_ahb.sv:106:-   logic [TAG-1:0]   slave_tag;
design/lib/axi4_to_ahb.sv:107:-   logic [63:0]      slave_rdata;
design/lib/axi4_to_ahb.sv:108:-   logic [3:0]       slave_opc;
design/lib/axi4_to_ahb.sv:109:-
design/lib/axi4_to_ahb.sv:110:-   logic             wrbuf_en, wrbuf_data_en;
design/lib/axi4_to_ahb.sv:111:-   logic             wrbuf_cmd_sent, wrbuf_rst;
design/lib/axi4_to_ahb.sv:112:-   logic             wrbuf_vld;
design/lib/axi4_to_ahb.sv:113:-   logic             wrbuf_data_vld;
design/lib/axi4_to_ahb.sv:114:-   logic [TAG-1:0]   wrbuf_tag;
design/lib/axi4_to_ahb.sv:115:-   logic [2:0]       wrbuf_size;
design/lib/axi4_to_ahb.sv:116:-   logic [31:0]      wrbuf_addr;
design/lib/axi4_to_ahb.sv:117:-   logic [63:0]      wrbuf_data;
design/lib/axi4_to_ahb.sv:118:-   logic [7:0]       wrbuf_byteen;
design/lib/axi4_to_ahb.sv:119:-
design/lib/axi4_to_ahb.sv:120:-   logic             master_valid;
design/lib/axi4_to_ahb.sv:121:-   logic             master_ready;
design/lib/axi4_to_ahb.sv:122:-   logic [TAG-1:0]   master_tag;
design/lib/axi4_to_ahb.sv:123:-   logic [31:0]      master_addr;
design/lib/axi4_to_ahb.sv:124:-   logic [63:0]      master_wdata;
design/lib/axi4_to_ahb.sv:125:-   logic [2:0]       master_size;
design/lib/axi4_to_ahb.sv:126:-   logic [2:0]       master_opc;
design/lib/axi4_to_ahb.sv:127:-   logic [7:0]       master_byteen;
design/lib/axi4_to_ahb.sv:128:-
design/lib/axi4_to_ahb.sv:129:-   // Buffer signals (one entry buffer)
design/lib/axi4_to_ahb.sv:130:-   logic [31:0]                buf_addr;
design/lib/axi4_to_ahb.sv:131:-   logic [1:0]                 buf_size;
design/lib/axi4_to_ahb.sv:132:-   logic                       buf_write;
design/lib/axi4_to_ahb.sv:133:-   logic [7:0]                 buf_byteen;
design/lib/axi4_to_ahb.sv:134:-   logic                       buf_aligned;
design/lib/axi4_to_ahb.sv:135:-   logic [63:0]                buf_data;
design/lib/axi4_to_ahb.sv:136:-   logic [TAG-1:0]             buf_tag;
design/lib/axi4_to_ahb.sv:137:-
design/lib/axi4_to_ahb.sv:138:-   //Miscellaneous signals
design/lib/axi4_to_ahb.sv:139:-   logic                       buf_rst;
design/lib/axi4_to_ahb.sv:140:-   logic [TAG-1:0]             buf_tag_in;
design/lib/axi4_to_ahb.sv:141:-   logic [31:0]                buf_addr_in;
design/lib/axi4_to_ahb.sv:142:-   logic [7:0]                 buf_byteen_in;
design/lib/axi4_to_ahb.sv:143:-   logic [63:0]                buf_data_in;
design/lib/axi4_to_ahb.sv:144:-   logic                       buf_write_in;
design/lib/axi4_to_ahb.sv:145:-   logic                       buf_aligned_in;
design/lib/axi4_to_ahb.sv:146:-   logic [2:0]                 buf_size_in;
design/lib/axi4_to_ahb.sv:147:-
design/lib/axi4_to_ahb.sv:148:-   logic                       buf_state_en;
design/lib/axi4_to_ahb.sv:149:-   logic                       buf_wr_en;
design/lib/axi4_to_ahb.sv:150:-   logic                       buf_data_wr_en;
design/lib/axi4_to_ahb.sv:151:-   logic                       slvbuf_error_en;
design/lib
localparam PRTY = 1;
typedef enum logic [2:0] {IDLE=3'b000, CMD_RD=3'b001, CMD_WR=3'b010, DATA_RD=3'b011, DATA_WR=3'b100, DONE=3'b101, STREAM_RD=3'b110, STREAM_ERR_RD=3'b111} state_t;
typedef enum logic [3:0] {
IDLE = 4'b0000,
CMD_RD = 4'b0001,
CMD_WR = 4'b1001,
DATA_RD = 4'b0010,
DATA_WR = 4'b1010,
DONE_RD = 4'b0011,
DONE_WR = 4'b1011,
STREAM_RD = 4'b0101,
STREAM_ERR_RD = 4'b0110
} state_t;

state_t buf_state, buf_nxtstate;

logic slave_valid;
logic slave_ready;
logic [TAG-1:0] slave_tag;
logic [63:0] slave_rdata;
logic [3:0] slave_opc;
Expand Down Expand Up @@ -217,7 +227,7 @@
found |= (byteen[j] & (3'(j) >= start_ptr[2:0])) ;
end
end
endfunction // get_nextbyte_ptr

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Raw Output:
design/lib/axi4_to_ahb.sv:230:-   endfunction // get_nextbyte_ptr
design/lib/axi4_to_ahb.sv:231:-
design/lib/axi4_to_ahb.sv:232:-   // Create bus synchronized version of force halt
design/lib/axi4_to_ahb.sv:233:-   assign dec_tlu_force_halt_bus = dec_tlu_force_halt | dec_tlu_force_halt_bus_q;
design/lib/axi4_to_ahb.sv:234:-   assign dec_tlu_force_halt_bus_ns = ~bus_clk_en & dec_tlu_force_halt_bus;
design/lib/axi4_to_ahb.sv:235:-   rvdff  #(.WIDTH(1))   force_halt_busff(.din(dec_tlu_force_halt_bus_ns), .dout(dec_tlu_force_halt_bus_q), .clk(free_clk), .*);
design/lib/axi4_to_ahb.sv:236:-
design/lib/axi4_to_ahb.sv:237:-   // Write buffer
design/lib/axi4_to_ahb.sv:238:-   assign wrbuf_en       = axi_awvalid & axi_awready & master_ready;
design/lib/axi4_to_ahb.sv:239:-   assign wrbuf_data_en  = axi_wvalid & axi_wready & master_ready;
design/lib/axi4_to_ahb.sv:240:-   assign wrbuf_cmd_sent = master_valid & master_ready & (master_opc[2:1] == 2'b01);
design/lib/axi4_to_ahb.sv:241:-   assign wrbuf_rst      = (wrbuf_cmd_sent & ~wrbuf_en) | dec_tlu_force_halt_bus;
design/lib/axi4_to_ahb.sv:242:-
design/lib/axi4_to_ahb.sv:243:-   assign axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent) & master_ready;
design/lib/axi4_to_ahb.sv:244:-   assign axi_wready  = ~(wrbuf_data_vld & ~wrbuf_cmd_sent) & master_ready;
design/lib/axi4_to_ahb.sv:245:-   assign axi_arready = ~(wrbuf_vld & wrbuf_data_vld) & master_ready;
design/lib/axi4_to_ahb.sv:246:-   assign axi_rlast   = 1'b1;
design/lib/axi4_to_ahb.sv:247:-
design/lib/axi4_to_ahb.sv:248:-   assign wr_cmd_vld          = (wrbuf_vld & wrbuf_data_vld);
design/lib/axi4_to_ahb.sv:249:-   assign master_valid        = wr_cmd_vld | axi_arvalid;
design/lib/axi4_to_ahb.sv:250:-   assign master_tag[TAG-1:0] = wr_cmd_vld ? wrbuf_tag[TAG-1:0] : axi_arid[TAG-1:0];
design/lib/axi4_to_ahb.sv:251:-   assign master_opc[2:0]     = wr_cmd_vld ? 3'b011 : 3'b0;
design/lib/axi4_to_ahb.sv:252:-   assign master_addr[31:0]   = wr_cmd_vld ? wrbuf_addr[31:0] : axi_araddr[31:0];
design/lib/axi4_to_ahb.sv:253:-   assign master_size[2:0]    = wr_cmd_vld ? wrbuf_size[2:0] : axi_arsize[2:0];
design/lib/axi4_to_ahb.sv:254:-   assign master_byteen[7:0]  = wrbuf_byteen[7:0];
design/lib/axi4_to_ahb.sv:255:-   assign master_wdata[63:0]  = wrbuf_data[63:0];
design/lib/axi4_to_ahb.sv:256:-
design/lib/axi4_to_ahb.sv:257:-   // AXI response channel signals
design/lib/axi4_to_ahb.sv:258:-   assign axi_bvalid       = slave_valid & slave_opc[3];
design/lib/axi4_to_ahb.sv:259:-   assign axi_bresp[1:0]   = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0);
design/lib/axi4_to_ahb.sv:260:-   assign axi_bid[TAG-1:0] = slave_tag[TAG-1:0];
design/lib/axi4_to_ahb.sv:261:-
design/lib/axi4_to_ahb.sv:262:-   assign axi_rvalid       = slave_valid & (slave_opc[3:2] == 2'b0);
design/lib/axi4_to_ahb.sv:263:-   assign axi_rresp[1:0]   = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0);
design/lib/axi4_to_ahb.sv:264:-   assign axi_rid[TAG-1:0] = slave_tag[TAG-1:0];
design/lib/axi4_to_ahb.sv:265:-   assign axi_rdata[63:0]  = slave_rdata[63:0];
design/lib/axi4_to_ahb.sv:266:-
design/lib/axi4_to_ahb.sv:267:- // FIFO state machine
design/lib/axi4_to_ahb.sv:268:-   always_comb begin
design/lib/axi4_to_ahb.sv:269:-      buf_nxtstate   = IDLE;
design/lib/axi4_to_ahb.sv:270:-      buf_state_en   = 1'b0;
design/lib/axi4_to_ahb.sv:271:-      buf_wr_en      = 1'b0;
design/lib/axi4_to_ahb.sv:272:-      buf_data_wr_en = 1'b0;
design/lib/axi4_to_ahb.sv:273:-      slvbuf_error_in   = 1'b0;
design/lib/axi4_to_ahb.sv:274:-      slvbuf_error_en   = 1'b0;
design/lib/axi4_to_ahb.sv:275:-      buf_write_in   = 1'b0;
design/lib/axi4_to_ahb.sv:276:-      cmd_done       = 1'b0;
design/lib/axi4_to_ahb.sv:277:-      trxn_done      = 1'b0;
design/lib/axi4_to_ahb.sv:278:-      buf_cmd_byte_ptr_en = 1'b0;
design/lib/axi4_to_ahb.sv:279:-      buf_cmd_byte_ptr[2:0] = '0;
design/lib/axi4_to_ahb.sv:280:-      slave_valid_pre   = 1'b0;
design/lib/axi4_to_ahb.sv:281:-      master_ready   = 1'b0;
design/lib/axi4_to_ahb.sv:282

// Create bus synchronized version of force halt
assign dec_tlu_force_halt_bus = dec_tlu_force_halt | dec_tlu_force_halt_bus_q;
Expand Down Expand Up @@ -245,15 +255,14 @@
assign master_wdata[63:0] = wrbuf_data[63:0];

// AXI response channel signals
assign axi_bvalid = slave_valid & slave_ready & slave_opc[3];
assign axi_bvalid = slave_valid & slave_opc[3];
assign axi_bresp[1:0] = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0);
assign axi_bid[TAG-1:0] = slave_tag[TAG-1:0];

assign axi_rvalid = slave_valid & slave_ready & (slave_opc[3:2] == 2'b0);
assign axi_rvalid = slave_valid & (slave_opc[3:2] == 2'b0);
assign axi_rresp[1:0] = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0);
assign axi_rid[TAG-1:0] = slave_tag[TAG-1:0];
assign axi_rdata[63:0] = slave_rdata[63:0];
assign slave_ready = axi_bready & axi_rready;

// FIFO state machine
always_comb begin
Expand Down Expand Up @@ -324,7 +333,7 @@
ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en}};
end
DATA_RD: begin
buf_nxtstate = DONE;
buf_nxtstate = DONE_RD;
buf_state_en = (ahb_hready_q | ahb_hresp_q);
buf_data_wr_en = buf_state_en;
slvbuf_error_in= ahb_hresp_q;
Expand All @@ -345,10 +354,10 @@
end
DATA_WR: begin
buf_state_en = (cmd_doneQ & ahb_hready_q) | ahb_hresp_q;
master_ready = buf_state_en & ~ahb_hresp_q & slave_ready; // Ready to accept new command if current command done and no error
buf_nxtstate = (ahb_hresp_q | ~slave_ready) ? DONE :
master_ready = buf_state_en & ~ahb_hresp_q & axi_bready; // Ready to accept new command if current command done and no error
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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]

buf_nxtstate = (ahb_hresp_q | ~axi_bready) ? DONE_WR :
((master_valid & master_ready) ? ((master_opc[2:1] == 2'b01) ? CMD_WR : CMD_RD) : IDLE);
slvbuf_error_in = ahb_hresp_q;

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Raw Output:
design/lib/axi4_to_ahb.sv:360:-                  slvbuf_error_in = ahb_hresp_q;
design/lib/axi4_to_ahb.sv:361:-                  slvbuf_error_en = buf_state_en;
design/lib/axi4_to_ahb.sv:362:-
design/lib/axi4_to_ahb.sv:363:-                  buf_write_in = (master_opc[2:1] == 2'b01);
design/lib/axi4_to_ahb.sv:364:-                  buf_wr_en = buf_state_en & ((buf_nxtstate == CMD_WR) | (buf_nxtstate == CMD_RD));
design/lib/axi4_to_ahb.sv:365:-                  buf_data_wr_en = buf_wr_en;
design/lib/axi4_to_ahb.sv:366:-
design/lib/axi4_to_ahb.sv:367:-                  cmd_done     = (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) &
design/lib/axi4_to_ahb.sv:368:-                                 ((buf_cmd_byte_ptrQ == 3'b111) | (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0))));
design/lib/axi4_to_ahb.sv:369:-                  bypass_en       = buf_state_en & buf_write_in & (buf_nxtstate == CMD_WR);   // Only bypass for writes for the time being
design/lib/axi4_to_ahb.sv:370:-                  ahb_htrans[1:0] = {2{(~(cmd_done | cmd_doneQ) | bypass_en)}} & 2'b10;
design/lib/axi4_to_ahb.sv:371:-                  slave_valid_pre  = buf_state_en & (buf_nxtstate != DONE_WR);
design/lib/axi4_to_ahb.sv:372:-
design/lib/axi4_to_ahb.sv:373:-                  trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0);
design/lib/axi4_to_ahb.sv:374:-                  buf_cmd_byte_ptr_en = trxn_done | bypass_en;
design/lib/axi4_to_ahb.sv:375:-                  buf_cmd_byte_ptr = bypass_en ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) :
design/lib/axi4_to_ahb.sv:376:-                                                 trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;
design/lib/axi4_to_ahb.sv:377:-         end
design/lib/axi4_to_ahb.sv:378:-         DONE_WR: begin
design/lib/axi4_to_ahb.sv:379:-                  buf_nxtstate = IDLE;
design/lib/axi4_to_ahb.sv:380:-                  buf_state_en = axi_bvalid & axi_bready;
design/lib/axi4_to_ahb.sv:381:-                  slvbuf_error_en = 1'b1;
design/lib/axi4_to_ahb.sv:382:-                  slave_valid_pre = 1'b1;
design/lib/axi4_to_ahb.sv:383:-         end
design/lib/axi4_to_ahb.sv:384:-         DONE_RD: begin
design/lib/axi4_to_ahb.sv:385:-                  buf_nxtstate = IDLE;
design/lib/axi4_to_ahb.sv:386:-                  buf_state_en = axi_rvalid & axi_rready; // axi_rlast == 1
design/lib/axi4_to_ahb.sv:387:-                  slvbuf_error_en = 1'b1;
design/lib/axi4_to_ahb.sv:388:-                  slave_valid_pre = 1'b1;
design/lib/axi4_to_ahb.sv:389:-         end
design/lib/axi4_to_ahb.sv:390:-         default: begin
design/lib/axi4_to_ahb.sv:391:-                  buf_nxtstate = IDLE;
design/lib/axi4_to_ahb.sv:392:-                  buf_state_en = 1'b1;
design/lib/axi4_to_ahb.sv:393:-         end
design/lib/axi4_to_ahb.sv:394:-      endcase
design/lib/axi4_to_ahb.sv:395:-   end
design/lib/axi4_to_ahb.sv:396:-
design/lib/axi4_to_ahb.sv:397:-   assign buf_rst              = dec_tlu_force_halt_bus;
design/lib/axi4_to_ahb.sv:398:-   assign cmd_done_rst         = slave_valid_pre;
design/lib/axi4_to_ahb.sv:399:-   assign buf_addr_in[31:3]    = master_addr[31:3];
design/lib/axi4_to_ahb.sv:400:-   assign buf_addr_in[2:0]     = (buf_aligned_in & (master_opc[2:1] == 2'b01)) ? get_write_addr(master_byteen[7:0]) : master_addr[2:0];
design/lib/axi4_to_ahb.sv:401:-   assign buf_tag_in[TAG-1:0]  = master_tag[TAG-1:0];
design/lib/axi4_to_ahb.sv:402:-   assign buf_byteen_in[7:0]   = wrbuf_byteen[7:0];
design/lib/axi4_to_ahb.sv:403:-   assign buf_data_in[63:0]    = (buf_state == DATA_RD) ? ahb_hrdata_q[63:0] : master_wdata[63:0];
design/lib/axi4_to_ahb.sv:404:-   assign buf_size_in[1:0]     = (buf_aligned_in & (master_size[1:0] == 2'b11) & (master_opc[2:1] == 2'b01)) ? get_write_size(master_byteen[7:0]) : master_size[1:0];
design/lib/axi4_to_ahb.sv:405:-   assign buf_aligned_in       = (master_opc[2:0] == 3'b0)    |   // reads are alw
slvbuf_error_en = buf_state_en;

buf_write_in = (master_opc[2:1] == 2'b01);
Expand All @@ -359,19 +368,29 @@
((buf_cmd_byte_ptrQ == 3'b111) | (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0))));
bypass_en = buf_state_en & buf_write_in & (buf_nxtstate == CMD_WR); // Only bypass for writes for the time being
ahb_htrans[1:0] = {2{(~(cmd_done | cmd_doneQ) | bypass_en)}} & 2'b10;
slave_valid_pre = buf_state_en & (buf_nxtstate != DONE);
slave_valid_pre = buf_state_en & (buf_nxtstate != DONE_WR);

trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0);
buf_cmd_byte_ptr_en = trxn_done | bypass_en;
buf_cmd_byte_ptr = bypass_en ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) :
trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;
end
DONE: begin
end
DONE_WR: begin
buf_nxtstate = IDLE;
buf_state_en = axi_bvalid & axi_bready;
slvbuf_error_en = 1'b1;
slave_valid_pre = 1'b1;
end
DONE_RD: begin
buf_nxtstate = IDLE;
buf_state_en = slave_ready;
buf_state_en = axi_rvalid & axi_rready; // axi_rlast == 1
slvbuf_error_en = 1'b1;
slave_valid_pre = 1'b1;
end
default: begin
buf_nxtstate = IDLE;
buf_state_en = 1'b1;
end
endcase
end

Expand All @@ -394,7 +413,7 @@
assign ahb_haddr[2:0] = {3{(ahb_htrans == 2'b10)}} & buf_cmd_byte_ptr[2:0]; // Trxn should be aligned during IDLE
assign ahb_hsize[2:0] = bypass_en ? {1'b0, ({2{buf_aligned_in}} & buf_size_in[1:0])} :
{1'b0, ({2{buf_aligned}} & buf_size[1:0])}; // Send the full size for aligned trxn
assign ahb_hburst[2:0] = 3'b0;

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Raw Output:
design/lib/axi4_to_ahb.sv:416:-   assign ahb_hburst[2:0] = 3'b0;
design/lib/axi4_to_ahb.sv:417:-   assign ahb_hmastlock   = 1'b0;
design/lib/axi4_to_ahb.sv:418:-   assign ahb_hprot[3:0]  = {3'b001,~axi_arprot[2]};
design/lib/axi4_to_ahb.sv:419:-   assign ahb_hwrite      = bypass_en ? (master_opc[2:1] == 2'b01) : buf_write;
design/lib/axi4_to_ahb.sv:420:-   assign ahb_hwdata[63:0] = buf_data[63:0];
design/lib/axi4_to_ahb.sv:421:-
design/lib/axi4_to_ahb.sv:422:-   assign slave_valid          = slave_valid_pre;// & (~slvbuf_posted_write | slvbuf_error);
design/lib/axi4_to_ahb.sv:423:-   assign slave_opc[3:2]       = slvbuf_write ? 2'b11 : 2'b00;
design/lib/axi4_to_ahb.sv:424:-   assign slave_opc[1:0]       = {2{slvbuf_error}} & 2'b10;
design/lib/axi4_to_ahb.sv:425:-   assign slave_rdata[63:0]    = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE_RD) ? buf_data[63:0] : ahb_hrdata_q[63:0]);
design/lib/axi4_to_ahb.sv:426:-   assign slave_tag[TAG-1:0]   = slvbuf_tag[TAG-1:0];
design/lib/axi4_to_ahb.sv:427:-
design/lib/axi4_to_ahb.sv:428:-   assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite ;
design/lib/axi4_to_ahb.sv:429:-
design/lib/axi4_to_ahb.sv:430:-
design/lib/axi4_to_ahb.sv:431:-   rvdffsc_fpga #(.WIDTH(1))   wrbuf_vldff     (.din(1'b1),              .dout(wrbuf_vld),          .en(wrbuf_en),      .clear(wrbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:432:-   rvdffsc_fpga #(.WIDTH(1))   wrbuf_data_vldff(.din(1'b1),              .dout(wrbuf_data_vld),     .en(wrbuf_data_en), .clear(wrbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:433:-   rvdffs_fpga  #(.WIDTH(TAG)) wrbuf_tagff     (.din(axi_awid[TAG-1:0]), .dout(wrbuf_tag[TAG-1:0]), .en(wrbuf_en),                         .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:434:-   rvdffs_fpga  #(.WIDTH(3))   wrbuf_sizeff    (.din(axi_awsize[2:0]),   .dout(wrbuf_size[2:0]),    .en(wrbuf_en),                         .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:435:-   rvdffe       #(.WIDTH(32))  wrbuf_addrff    (.din(axi_awaddr[31:0]),  .dout(wrbuf_addr[31:0]),   .en(wrbuf_en & bus_clk_en),            .clk(clk), .*);
design/lib/axi4_to_ahb.sv:436:-   rvdffe       #(.WIDTH(64))  wrbuf_dataff    (.din(axi_wdata[63:0]),   .dout(wrbuf_data[63:0]),   .en(wrbuf_data_en & bus_clk_en),       .clk(clk), .*);
design/lib/axi4_to_ahb.sv:437:-   rvdffs_fpga  #(.WIDTH(8))   wrbuf_byteenff  (.din(axi_wstrb[7:0]),    .dout(wrbuf_byteen[7:0]),  .en(wrbuf_data_en),                    .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:438:-
design/lib/axi4_to_ahb.sv:439:-   rvdffs_fpga #(.WIDTH(32))   last_bus_addrff (.din(ahb_haddr[31:0]),   .dout(last_bus_addr[31:0]), .en(last_addr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:440:-
design/lib/axi4_to_ahb.sv:441:-   rvdffsc_fpga #(.WIDTH($bits(state_t))) buf_state_ff  (.din(buf_nxtstate),        .dout({buf_state}),      .en(buf_state_en), .clear(buf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:442:-   rvdffs_fpga #(.WIDTH(1))               buf_writeff   (.din(buf_write_in),        .dout(buf_write),        .en(buf_wr_en),                     .clk(buf_clk), .clken(buf_clken),  .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:443:-   rvdffs_fpga #(.WIDTH(TAG))             buf_tagff     (.din(buf_tag_in[TAG-1:0]), .dout(buf_tag[TAG-1:0]), .en(buf_wr_en),                     .clk(buf_clk), .clken(buf_clken),  .rawclk(clk), .*);
design/lib/axi4_to_ahb.sv:444:-   rvdffe      #(.WIDTH(32))              buf_addrff    (.din(buf_addr_in[31:0]),   .dout(buf_addr[31:0]),   .en(buf_wr_en & bus_clk_en),        .clk(clk), .*);
design/lib/axi4_to_ahb.sv:445:-   rvdffs_fpga #(.WIDTH(2))               buf_sizeff    (.din(buf_size_in[1:0]),    .dout(buf_size[1:0]),    .en(buf_wr_en),                     .clk(buf_c
assign ahb_hmastlock = 1'b0;
assign ahb_hprot[3:0] = {3'b001,~axi_arprot[2]};
assign ahb_hwrite = bypass_en ? (master_opc[2:1] == 2'b01) : buf_write;
Expand All @@ -403,7 +422,7 @@
assign slave_valid = slave_valid_pre;// & (~slvbuf_posted_write | slvbuf_error);
assign slave_opc[3:2] = slvbuf_write ? 2'b11 : 2'b00;
assign slave_opc[1:0] = {2{slvbuf_error}} & 2'b10;
assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE) ? buf_data[63:0] : ahb_hrdata_q[63:0]);
assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE_RD) ? buf_data[63:0] : ahb_hrdata_q[63:0]);
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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 138 [Style: line-length] [line-length]

assign slave_tag[TAG-1:0] = slvbuf_tag[TAG-1:0];

assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite ;
Expand Down
7 changes: 7 additions & 0 deletions testbench/tb_top.sv
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -328,8 +328,15 @@ module tb_top (

`define DEC rvtop.veer.dec

`ifdef RV_BUILD_AXI4
assign mailbox_write = lmem.awvalid && lmem.awaddr == mem_mailbox && rst_l;
assign mailbox_data = lmem.wdata;
`endif
`ifdef RV_BUILD_AHB_LITE
assign mailbox_write = lmem.write && lmem.laddr == mem_mailbox && rst_l;
assign mailbox_data = lmem.HWDATA;
`endif

assign mailbox_data_val = mailbox_data[7:0] > 8'h5 && mailbox_data[7:0] < 8'h7f;

parameter MAX_CYCLES = 2_000_000;
Expand Down
2 changes: 1 addition & 1 deletion tools/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
# limitations under the License.
#

CONF_PARAMS = -set build_axi4
CONF_PARAMS ?= -set build_axi4

TEST_CFLAGS = -g -O3 -funroll-all-loops
ABI = -mabi=ilp32 -march=rv32imac
Expand Down
7 changes: 4 additions & 3 deletions verification/block/lib_axi4_to_ahb/axi_r_bfm.py
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -109,9 +109,10 @@ async def rsp_monitor_q_bfm(self):
await RisingEdge(self.rst_n)
await RisingEdge(self.clk)
if get_int(self.dut.axi_rvalid):
sigs = get_signals(AXI_R_CHAN_RSP_SIGNALS, self.dut)
values = tuple(sig.value for sig in sigs)
await self.rsp_monitor_q.put(values)
if get_int(self.dut.axi_rready):
sigs = get_signals(AXI_R_CHAN_RSP_SIGNALS, self.dut)
values = tuple(sig.value for sig in sigs)
await self.rsp_monitor_q.put(values)

def start_bfm(self):
cocotb.start_soon(self.drive())
Expand Down
6 changes: 5 additions & 1 deletion verification/block/lib_axi4_to_ahb/coordinator_seq.py
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
import cocotb
from ahb_lite_pkg import AHB_LITE_NOTIFICATION
from ahb_lite_seq import AHBLiteAcceptReadSeq, AHBLiteAcceptWriteSeq
from axi_r_seq import AXIReadTransactionRequestSeq
from axi_r_seq import AXIReadTransactionRequestSeq, AXIReadTransactionResponseSeq
from axi_w_seq import (
AXIWriteDataSeq,
AXIWriteResponseSeq,
Expand Down Expand Up @@ -37,6 +37,7 @@ async def axi_write(self, axi_seqr, ahb_seqr):

async def axi_read(self, axi_seqr, ahb_seqr):
axi_trq_seq = AXIReadTransactionRequestSeq()
axi_rresp_seq = AXIReadTransactionResponseSeq()

# Read Request
await axi_trq_seq.start(axi_seqr)
Expand All @@ -46,6 +47,9 @@ async def axi_read(self, axi_seqr, ahb_seqr):
await self.ahb_response_handler(ahb_seqr=ahb_seqr, is_read=True)
await self.delay(5)

# Read Response
await axi_rresp_seq.start(axi_seqr)

async def delay(self, i):
for _ in range(i):
await RisingEdge(cocotb.top.clk)
Expand Down
39 changes: 1 addition & 38 deletions verification/block/lib_axi4_to_ahb/test_axi.py
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Original file line number Diff line number Diff line change
Expand Up @@ -6,45 +6,8 @@
from coordinator_seq import TestBothChannelsSeq
from testbench import BaseTest

# FIXME : This test is expected to fail.
# Reason : Handshake sequence is non-compliant with specification
# Faulty code : axi4_to_ahb.sv#L248-256
#
# Issue #1 BVALID/BREADY Handshake
# Handshake is meant to occur on the Write Response Channel in order:
# * subordinate asserts BVALID
# * manager responds with BREADY
# Quote: "The Subordinate must not wait for the Manager to assert BREADY
# before asserting BVALID"
# Source: AMBA AXI Protocol Specification A3.5.1 Write transaction dependencies
#
# In RTL:
#
# assign axi_bvalid = slave_valid & slave_ready & slave_opc[3];
# assign slave_ready = axi_bready & axi_rready;
#
# BVALID is calculated from BREADY and RREADY, which is wrong for 2 reasons:
# * BVALID should not depend on RREADY
# * BVALID should be asserted before BREADY. BREADY should depend on BVALID.
#
# Issue #2 RVALID/RREADY Handshake
# Handshake is meant to occur on the Read Response Channel in order:
# * subordinate asserts RVALID
# * manager responds with RREADY
# Quote: "The Subordinate must not wait for the Manager to assert RREADY
# before asserting RVALID"
# Source: AMBA AXI Protocol Specification A3.5.2 Read transaction dependencies
#
# In RTL:
# assign axi_rvalid = slave_valid & slave_ready & (slave_opc[3:2] == 2'b0);
# assign slave_ready = axi_bready & axi_rready;
#
# RVALID is calculated from BREADY and RREADY, which is wrong for 2 reasons:
# * RVALID should not depend on BREADY
# * RVALID should be asserted before RREADY. RREADY should depend on RVALID.


@pyuvm.test(expect_error=(TimeoutError, QueueFull))
@pyuvm.test()
class TestAXI(BaseTest):
def end_of_elaboration_phase(self):
self.seq = TestBothChannelsSeq.create("stimulus")
Expand Down
5 changes: 1 addition & 4 deletions verification/block/lib_axi4_to_ahb/test_axi_read_channel.py
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Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,8 @@
from coordinator_seq import TestReadChannelSeq
from testbench import BaseTest

# FIXME : This test is expected to fail.
# See description in `test_axi.py`


@pyuvm.test(expect_error=QueueFull)
@pyuvm.test()
class TestAXIReadChannel(BaseTest):
def end_of_elaboration_phase(self):
self.seq = TestReadChannelSeq.create("stimulus")
Expand Down
5 changes: 1 addition & 4 deletions verification/block/lib_axi4_to_ahb/test_axi_write_channel.py
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Original file line number Diff line number Diff line change
Expand Up @@ -5,11 +5,8 @@
from coordinator_seq import TestWriteChannelSeq
from testbench import BaseTest

# FIXME : This test is expected to fail.
# See description in `test_axi.py`


@pyuvm.test(expect_error=TimeoutError)
@pyuvm.test()
class TestAXIWriteChannel(BaseTest):
def end_of_elaboration_phase(self):
self.seq = TestWriteChannelSeq.create("stimulus")
Expand Down
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