Microarchitectural tests for DMA controller #118
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Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Internal-tag: [#48921] Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
…loading them as artifacts Signed-off-by: Maciej Kurc <[email protected]>
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Signed-off-by: Maciej Kurc <[email protected]>
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Links to coverage and verification reports for this PR (#118) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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This PR adds tests for the DMA port controller. The tests are written according to UVM methodology using
pyuvm.