Microarchitectural tests for PIC #116
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Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
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Signed-off-by: Maciej Kurc <[email protected]>
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Links to coverage and verification reports for this PR (#116) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#116) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#116) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Signed-off-by: Maciej Kurc <[email protected]>
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Links to coverage and verification reports for this PR (#116) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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LGTM |
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This PR adds microarchitectural tests for the PIC. The tests are written in Python using the
pyvumframework. This makes them architecturally compatible with UVM.The tests are run in the CI by the added
test-uarch.ymlworkflow. Coverage data is collected and aggregated with data obtained from existing tests.