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export icache signals
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@wsipak
wsipak committed Nov 13, 2024
1 parent 79765ce commit f602924
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28 changes: 18 additions & 10 deletions design/el2_mem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -62,8 +62,8 @@ import el2_pkg::*;
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
// input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
// input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,

input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
Expand All @@ -83,7 +83,8 @@ import el2_pkg::*;
output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error

el2_mem_if.veer_sram_src mem_export,
el2_mem_if.veer_sram_src mem_export,
el2_mem_if.veer_icache_src icache_export,

input logic scan_mode

Expand All @@ -95,6 +96,7 @@ import el2_pkg::*;
el2_mem_if mem_export_local ();

assign mem_export .clk = clk;
assign icache_export .clk = clk;
assign mem_export_local.clk = clk;

assign mem_export .iccm_clken = mem_export_local.iccm_clken;
Expand All @@ -114,13 +116,19 @@ import el2_pkg::*;
assign mem_export_local.dccm_bank_ecc = mem_export .dccm_bank_ecc;

// icache data
assign mem_export .icache_bank_way_clken = mem_export_local.icache_bank_way_clken;
assign mem_export .icache_b_sb_wren = mem_export_local.icache_b_sb_wren;
assign mem_export_local.icache_wb_dout = mem_export.icache_wb_dout;
assign icache_export .icache_bank_way_clken = mem_export_local.icache_bank_way_clken;
assign icache_export .icache_b_sb_wren = mem_export_local.icache_b_sb_wren;
assign icache_export .icache_sb_wr_data = mem_export_local.icache_sb_wr_data;
assign icache_export .icache_bank_wr_data = mem_export_local.icache_bank_wr_data;
assign icache_export .icache_rw_addr_bank_q = mem_export_local.icache_rw_addr_bank_q;
assign mem_export_local.icache_wb_dout = icache_export.icache_wb_dout;
assign mem_export_local.icache_wb_dout_ecc_bank = icache_export.icache_wb_dout_ecc_bank;
// icache tag
assign mem_export .icache_tag_clken = mem_export_local.icache_tag_clken;
assign mem_export .icache_tag_data_raw = mem_export_local.icache_tag_data_raw;

assign icache_export .icache_tag_clken = mem_export_local.icache_tag_clken;
assign icache_export .icache_tag_data_raw = mem_export_local.icache_tag_data_raw;
assign icache_export .icache_tag_wren_q = mem_export_local.icache_tag_wren_q;
assign icache_export .icache_tag_wr_data = mem_export_local.icache_tag_wr_data;
assign icache_export .icache_tag_rw_addr_q = mem_export_local.icache_tag_rw_addr_q;

assign mem_export_local.clk = clk;
// TODO assign all signals from modport veer_icache_src (lib/el2_mem_if.sv)
Expand All @@ -140,7 +148,7 @@ import el2_pkg::*;
if ( pt.ICACHE_ENABLE ) begin: icache
el2_ifu_ic_mem #(.pt(pt)) icm (
.clk_override(icm_clk_override),
.icache_export(mem_export_local.veer_icache)
.icache_export(mem_export_local.veer_icache),
.*
);

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design/el2_mem.sv:153:-   );
design/el2_mem.sv:154:-end
design/el2_mem.sv:155:-else  begin
design/el2_mem.sv:156:-   assign   ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0;
design/el2_mem.sv:157:-   assign   ic_tag_perr    = '0 ;
design/el2_mem.sv:158:-   assign   ic_rd_data  = '0 ;
design/el2_mem.sv:159:-   assign   ictag_debug_rd_data  = '0 ;
design/el2_mem.sv:160:-   assign   ic_debug_rd_data  = '0 ;
design/el2_mem.sv:161:-   assign   ic_eccerr      = '0;
design/el2_mem.sv:162:-end // else: !if( pt.ICACHE_ENABLE )
design/el2_mem.sv:163:-
design/el2_mem.sv:164:-
design/el2_mem.sv:165:-
design/el2_mem.sv:166:-if (pt.ICCM_ENABLE) begin : iccm
design/el2_mem.sv:167:-   el2_ifu_iccm_mem  #(.pt(pt)) iccm (.*,
design/el2_mem.sv:168:-                  .clk_override(icm_clk_override),
design/el2_mem.sv:169:-                  .iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]),
design/el2_mem.sv:170:-                  .iccm_rd_data(iccm_rd_data[63:0]),
design/el2_mem.sv:171:-                  .iccm_mem_export(mem_export_local.veer_iccm)
design/el2_mem.sv:172:-                   );
design/el2_mem.sv:173:-end
design/el2_mem.sv:174:-else  begin
design/el2_mem.sv:175:-   assign  iccm_rd_data    = '0 ;
design/el2_mem.sv:176:-   assign iccm_rd_data_ecc = '0 ;
design/el2_mem.sv:177:-end
design/el2_mem.sv:97:+  );
design/el2_mem.sv:98:+
design/el2_mem.sv:99:+  el2_mem_if mem_export_local ();
design/el2_mem.sv:100:+
design/el2_mem.sv:101:+  assign mem_export.clk                           = clk;
design/el2_mem.sv:102:+  assign icache_export.clk                        = clk;
design/el2_mem.sv:103:+  assign mem_export_local.clk                     = clk;
design/el2_mem.sv:104:+
design/el2_mem.sv:105:+  assign mem_export.iccm_clken                    = mem_export_local.iccm_clken;
design/el2_mem.sv:106:+  assign mem_export.iccm_wren_bank                = mem_export_local.iccm_wren_bank;
design/el2_mem.sv:107:+  assign mem_export.iccm_addr_bank                = mem_export_local.iccm_addr_bank;
design/el2_mem.sv:108:+  assign mem_export.iccm_bank_wr_data             = mem_export_local.iccm_bank_wr_data;
design/el2_mem.sv:109:+  assign mem_export.iccm_bank_wr_ecc              = mem_export_local.iccm_bank_wr_ecc;
design/el2_mem.sv:110:+  assign mem_export_local.iccm_bank_dout          = mem_export.iccm_bank_dout;
design/el2_mem.sv:111:+  assign mem_export_local.iccm_bank_ecc           = mem_export.iccm_bank_ecc;
design/el2_mem.sv:112:+
design/el2_mem.sv:113:+  assign mem_export.dccm_clken                    = mem_export_local.dccm_clken;
design/el2_mem.sv:114:+  assign mem_export.dccm_wren_bank                = mem_export_local.dccm_wren_bank;
design/el2_mem.sv:115:+  assign mem_export.dccm_addr_bank                = mem_export_local.dccm_addr_bank;
design/el2_mem.sv:116:+  assign mem_export.dccm_wr_data_bank             = mem_export_local.dccm_wr_data_bank;
design/el2_mem.sv:117:+  assign mem_export.dccm_wr_ecc_bank              = mem_export_local.dccm_wr_ecc_bank;
design/el2_mem.sv:118:+  assign mem_export_local.dccm_bank_dout          = mem_export.dccm_bank_dout;
design/el2_mem.sv:119:+  assign mem_export_local.dccm_bank_ecc           = mem_export.dccm_bank_ecc;
design/el2_mem.sv:120:+
design/el2_mem.sv:121:+  // icache data
design/el2_mem.sv:122:+  assign icache_export.icache_bank_way_clken      = mem_export_local.icache_bank_way_clken;
design/el2_mem.sv:123:+  assign icache_export.icache_b_sb_wren           = mem_export_local.icache_b_sb_wren;
design/el2_mem.sv:124:+  assign icache_export.icache_sb_wr_data          = mem_export_local.icache_sb_wr_data;
design/el2_mem.sv:125:+  assign icache_export.icache_bank_wr_data        = mem_export_local.icache_bank_wr_data;
design/el2_mem.sv:126:+  assign icache_export.icache_rw_addr_bank_q      = mem_export_local.icache_rw_addr_bank_q;
design/el2_mem.sv:127:+  assign mem_export_local.icache_wb_dout          = icache_export.icache_wb_dout;
design/el2_mem.sv:128:+  assign mem_export_local.icache_wb_dout_ecc_bank = icache_export.icache_wb_dout_ecc_bank
end
Expand Down
3 changes: 1 addition & 2 deletions design/el2_veer_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -393,9 +393,8 @@ import el2_pkg::*;
// input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,

// ICache export interfaces
el2_mem_if.veer_icache el2_icache_export,
el2_mem_if.veer_icache_src el2_icache_export,


input logic timer_int,
input logic soft_int,
input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
Expand Down
87 changes: 46 additions & 41 deletions design/ifu/el2_ifu_ic_mem.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -200,7 +200,11 @@ import el2_pkg::*;
// Expose the ICACHE DATA signals outside of the core.
always_comb begin
icache_export.icache_bank_way_clken = ic_bank_way_clken;
icache_export.icache_b_sb_ren = ic_b_sb_ren;
icache_export.icache_b_sb_wren = ic_b_sb_wren;
icache_export.icache_sb_wr_data = ic_sb_wr_data;
icache_export.icache_bank_wr_data = ic_bank_wr_data;
icache_export.icache_rw_addr_bank_q = ic_rw_addr_bank_q;
wb_dout_ecc_bank = icache_export.icache_wb_dout_ecc_bank;
wb_dout = icache_export.icache_wb_dout;
end

Expand Down Expand Up @@ -273,17 +277,17 @@ import el2_pkg::*;
.Q (wb_dout_pre_up[i][k]), \
.CLK (clk), \
.ROP ( ), \
.TEST1(ic_data_ext_in_pkt[i][k].TEST1), \
.RME(ic_data_ext_in_pkt[i][k].RME), \
.RM(ic_data_ext_in_pkt[i][k].RM), \
.TEST1(), \
.RME(), \
.RM(), \
\
.LS(ic_data_ext_in_pkt[i][k].LS), \
.DS(ic_data_ext_in_pkt[i][k].DS), \
.SD(ic_data_ext_in_pkt[i][k].SD), \
.LS(), \
.DS(), \
.SD(), \
\
.TEST_RNM(ic_data_ext_in_pkt[i][k].TEST_RNM), \
.BC1(ic_data_ext_in_pkt[i][k].BC1), \
.BC2(ic_data_ext_in_pkt[i][k].BC2) \
.TEST_RNM(), \
.BC1(), \
.BC2() \
); \
if (pt.ICACHE_BYPASS_ENABLE == 1) begin \
assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (pt.ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); \
Expand Down Expand Up @@ -425,17 +429,17 @@ if (pt.ICACHE_BYPASS_ENABLE == 1) begin \
.Q (wb_packeddout_pre[k]), \
.ME (|ic_bank_way_clken_final[k]), \
.ROP ( ), \
.TEST1 (ic_data_ext_in_pkt[0][k].TEST1), \
.RME (ic_data_ext_in_pkt[0][k].RME), \
.RM (ic_data_ext_in_pkt[0][k].RM), \
.TEST1 (), \
.RME (), \
.RM (), \
\
.LS (ic_data_ext_in_pkt[0][k].LS), \
.DS (ic_data_ext_in_pkt[0][k].DS), \
.SD (ic_data_ext_in_pkt[0][k].SD), \
.LS (), \
.DS (), \
.SD (), \
\
.TEST_RNM (ic_data_ext_in_pkt[0][k].TEST_RNM), \
.BC1 (ic_data_ext_in_pkt[0][k].BC1), \
.BC2 (ic_data_ext_in_pkt[0][k].BC2) \
.TEST_RNM (), \
.BC1 (), \
.BC2 () \
); \
\
if (pt.ICACHE_BYPASS_ENABLE == 1) begin \
Expand Down Expand Up @@ -867,12 +871,13 @@ import el2_pkg::*;
logic ic_rd_en_ff;
logic ic_tag_parity;


// TODO Do we need to move this to a GENVAR block and iterate over banks, assign them with indexing?
// Expose the ICACHE TAG signals outside of the core.
always_comb begin
icache_export.icache_tag_clken = ic_tag_clken;
icache_export.icache_tag_data_raw = ic_tag_data_raw;
icache_export.icache_tag_clken = ic_tag_clken;
icache_export.icache_tag_data_raw = ic_tag_data_raw;
icache_export.icache_tag_wren_q = ic_tag_wren_q;
icache_export.icache_tag_wr_data = ic_tag_wr_data;
icache_export.icache_tag_rw_addr_q = ic_rw_addr_q;
end

assign ic_tag_wren [pt.ICACHE_NUM_WAYS-1:0] = ic_wr_en[pt.ICACHE_NUM_WAYS-1:0] & {pt.ICACHE_NUM_WAYS{(ic_rw_addr[pt.ICACHE_BEAT_ADDR_HI:4] == {pt.ICACHE_BEAT_BITS-1{1'b1}})}} ;
Expand Down Expand Up @@ -991,17 +996,17 @@ end // block: OTHERS
.CLK (clk), \
.ROP ( ), \
\
.TEST1(ic_tag_ext_in_pkt[i].TEST1), \
.RME(ic_tag_ext_in_pkt[i].RME), \
.RM(ic_tag_ext_in_pkt[i].RM), \
.TEST1(), \
.RME(), \
.RM(), \
\
.LS(ic_tag_ext_in_pkt[i].LS), \
.DS(ic_tag_ext_in_pkt[i].DS), \
.SD(ic_tag_ext_in_pkt[i].SD), \
.LS(), \
.DS(), \
.SD(), \
\
.TEST_RNM(ic_tag_ext_in_pkt[i].TEST_RNM), \
.BC1(ic_tag_ext_in_pkt[i].BC1), \
.BC2(ic_tag_ext_in_pkt[i].BC2) \
.TEST_RNM(), \
.BC1(), \
.BC2() \
\
); \
\
Expand Down Expand Up @@ -1195,17 +1200,17 @@ end // block: OTHERS
.CLK (clk), \
.ROP ( ), \
\
.TEST1 (ic_tag_ext_in_pkt[0].TEST1), \
.RME (ic_tag_ext_in_pkt[0].RME), \
.RM (ic_tag_ext_in_pkt[0].RM), \
.TEST1 (), \
.RME (), \
.RM (), \
\
.LS (ic_tag_ext_in_pkt[0].LS), \
.DS (ic_tag_ext_in_pkt[0].DS), \
.SD (ic_tag_ext_in_pkt[0].SD), \
.LS (), \
.DS (), \
.SD (), \
\
.TEST_RNM (ic_tag_ext_in_pkt[0].TEST_RNM), \
.BC1 (ic_tag_ext_in_pkt[0].BC1), \
.BC2 (ic_tag_ext_in_pkt[0].BC2) \
.TEST_RNM (), \
.BC1 (), \
.BC2 () \
\
); \
\
Expand Down
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