Skip to content

Commit

Permalink
Add missing DMI mux signals
Browse files Browse the repository at this point in the history
Internal-tag: [#52028]
Signed-off-by: Robert Szczepanski <[email protected]>
  • Loading branch information
robertszczepanski committed Jan 5, 2024
1 parent 94dbab8 commit cb75d78
Show file tree
Hide file tree
Showing 4 changed files with 29 additions and 17 deletions.
3 changes: 2 additions & 1 deletion design/dmi/dmi_mux.v
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
module dmi_mux (

// Uncore access enable
input wire uncore_enable,
input wire uncore_enable,

// DMI upstream
input wire dmi_en,
Expand All @@ -27,6 +27,7 @@ module dmi_mux (
output wire [31:0] dmi_uncore_wdata,
input wire [31:0] dmi_uncore_rdata
);
logic is_uncore_aperture;

// Uncore address decoder
assign is_uncore_aperture = (dmi_addr[6] & (dmi_addr[5] | dmi_addr[4]));
Expand Down
24 changes: 10 additions & 14 deletions design/el2_veer_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -335,11 +335,12 @@ import el2_pkg::*;
input logic mbist_mode, // to enable mbist

// DMI port for uncore
input logic dmi_uncore_enable,
output logic dmi_uncore_en,
output logic dmi_uncore_wr_en,
output logic dmi_uncore_addr,
output logic dmi_uncore_wdata,
input logic dmi_uncore_rdata
output logic [ 6:0] dmi_uncore_addr,
output logic [31:0] dmi_uncore_wdata,
input logic [31:0] dmi_uncore_rdata
);

logic active_l2clk;

Check warning on line 346 in design/el2_veer_wrapper.sv

View workflow job for this annotation

GitHub Actions / format-review

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:346:- logic active_l2clk; design/el2_veer_wrapper.sv:347:- logic free_l2clk; design/el2_veer_wrapper.sv:345:+ logic active_l2clk; design/el2_veer_wrapper.sv:346:+ logic free_l2clk;
Expand Down Expand Up @@ -701,13 +702,6 @@ import el2_pkg::*;
logic [31:0] dmi_reg_wdata;
logic [31:0] dmi_reg_rdata;

// DMI (uncore)
logic dmi_uncore_en;
logic [6:0] dmi_uncore_addr;
logic dmi_uncore_wr_en;
logic [31:0] dmi_uncore_wdata;
logic [31:0] dmi_uncore_rdata;

// Instantiate the el2_veer core
el2_veer #(.pt(pt)) veer (
.clk(clk),
Expand Down Expand Up @@ -746,6 +740,8 @@ import el2_pkg::*;

// DMI core/uncore mux
dmi_mux dmi_mux (
.uncore_enable (dmi_uncore_enable),

.dmi_en (dmi_en),
.dmi_wr_en (dmi_wr_en),
.dmi_addr (dmi_addr),
Expand All @@ -766,11 +762,11 @@ import el2_pkg::*;
);

`ifdef RV_ASSERT_ON
// to avoid internal assertions failure at time 0
initial begin
// to avoid internal assertions failure at time 0
initial begin
$assertoff(0, veer);
@ (negedge clk) $asserton(0, veer);
end
@(negedge clk) $asserton(0, veer);
end
`endif

endmodule
9 changes: 8 additions & 1 deletion testbench/tb_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -802,7 +802,14 @@ veer_wrapper rvtop_wrapper (
.soft_int ('0),
.core_id ('0),
.scan_mode ( 1'b0 ), // To enable scan mode
.mbist_mode ( 1'b0 ) // to enable mbist
.mbist_mode ( 1'b0 ), // to enable mbist

.dmi_uncore_enable (),
.dmi_uncore_en (),
.dmi_uncore_wr_en (),
.dmi_uncore_addr (),
.dmi_uncore_wdata (),
.dmi_uncore_rdata ()

);

Expand Down
10 changes: 9 additions & 1 deletion testbench/veer_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -341,7 +341,15 @@ module veer_wrapper
input logic i_cpu_run_req, // Async restart req to CPU
output logic o_cpu_run_ack, // Core response to run req
input logic scan_mode, // To enable scan mode
input logic mbist_mode // to enable mbist
input logic mbist_mode, // to enable mbist

// DMI port for uncore
input logic dmi_uncore_enable,
output logic dmi_uncore_en,
output logic dmi_uncore_wr_en,
output logic [ 6:0] dmi_uncore_addr,
output logic [31:0] dmi_uncore_wdata,
input logic [31:0] dmi_uncore_rdata
);

el2_mem_if mem_export ();
Expand Down

0 comments on commit cb75d78

Please sign in to comment.