Merge pull request #201 from antmicro/61959-add-bitmanip-dv

tools/riscv-dv: add bitmanip tests
chipsalliance · Aug 6, 2024 · 6f07862 · 6f07862
2 parents 5c9580f + fb554b5
commit 6f07862
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Showing 5 changed files with 54 additions and 5 deletions.
diff --git a/.github/workflows/test-riscv-dv.yml b/.github/workflows/test-riscv-dv.yml
@@ -200,7 +200,7 @@ jobs:
         test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
         iss:
           - spike
-          - whisper
+#         - whisper
 #         - renode
         coverage: ["all", "branch", "toggle"] #TODO: add functional coverage
         version: [ uvm ]
@@ -237,9 +237,18 @@ jobs:
         run: |
           sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
             git cpanminus ccache device-tree-compiler python3-minimal python3-pip \
-            libboost-all-dev gcc-riscv64-unknown-elf
+            libboost-all-dev
           sudo cpanm Bit::Vector
 
+      # As of July 9th, 2024 `ubuntu:latest` comes with riscv64-unknown-elf-gcc
+      # 10.0.2. We need a newer version for bitmanip extension support.
+      - name: Install cross-compiler
+        run: |
+          echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
+          sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
+            gcc-riscv64-unknown-elf
+          riscv64-unknown-elf-gcc --version
+
       - name: Setup Cache Metadata
         id: cache_metadata
         run: |

diff --git a/third_party/riscv-dv b/third_party/riscv-dv
diff --git a/tools/riscv-dv/Makefile b/tools/riscv-dv/Makefile
@@ -68,7 +68,8 @@ RISCV_DV_ARGS = \
     --start_seed $(RISCV_DV_SEED) \
     --iterations $(RISCV_DV_ITER) \
     --batch_size $(RISCV_DV_BATCH) \
-    --isa rv32imc --mabi ilp32 \
+    --isa rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs \
+    --mabi ilp32 \
     --custom_target $(PWD) \
     --testlist $(PWD)/testlist.yaml \
     -v -o $(TEST_DIR)

diff --git a/tools/riscv-dv/riscv_core_setting.sv b/tools/riscv-dv/riscv_core_setting.sv
@@ -13,7 +13,17 @@ privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
 riscv_instr_name_t unsupported_instr[] = {
     NOP, // RV32I
     CLZ, // RV32ZBB
-    SROI, CMIX, FSRI, FSR, CMOV, SRO, SLO, FSL, SLOI // RV32B
+    SROI, CMIX, FSRI, FSR, CMOV, SRO, SLO, FSL, SLOI, // RV32B
+    // FIXME: As of date, the decision on which bitmanip extensions should go
+    // into the `B` collection is not yet ratified.
+    //
+    // To stay on the safe side, let's assume here that *all of them* are
+    // enabled by the `B` extension collection.
+    CRC32C_B, CRC32C_H, CRC32C_W, CRC32_B, CRC32_H, CRC32_W, // RV32ZBR
+    GORC, GORCI, GREV, GREVI, SHFL, SHFLI, UNSHFL, UNSHFLI, // RV32ZBP
+    BCOMPRESS, BDECOMPRESS, // RV32ZBE
+    BFP, // RV32ZBF
+    XPERM_B, XPERM_H, XPERM_N // RV32ZBP
 };
 
 // ISA supported by the processor

diff --git a/tools/riscv-dv/testlist.yaml b/tools/riscv-dv/testlist.yaml
@@ -97,3 +97,32 @@
     +is_timeout_s_fatal=0
     +enable_bad_intg_on_uninit_access=0
   rtl_test: core_base_test
+
+- test: riscv_bitmanip_full_test_veer
+  desc: >
+    Random instruction test with supported B extension instructions in full
+    configuration.
+  iterations: 10
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +enable_zba_extension=1
+    +enable_zbb_extension=1
+    +enable_zbc_extension=1
+    +enable_zbs_extension=1
+    +enable_b_extension=1
+    +enable_bitmanip_groups=zbe,zbf,zbp,zbr,zbt
+  rtl_test: core_base_test
+
+- test: riscv_bitmanip_balanced_test_veer
+  desc: >
+    Random instruction test with supported B extension instructions in
+    balanced configuration.
+  iterations: 10
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +enable_zba_extension=1
+    +enable_zbb_extension=1
+    +enable_zbs_extension=1
+    +enable_b_extension=1
+    +enable_bitmanip_groups=zbf,zbt
+  rtl_test: core_base_test