remove ext_in_pkt interfaces for icache

chipsalliance · Nov 22, 2024 · 6a09e08 · 6a09e08
1 parent fdcc507
commit 6a09e08
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Showing 5 changed files with 0 additions and 19 deletions.
diff --git a/design/el2_mem.sv b/design/el2_mem.sv
@@ -62,8 +62,6 @@ import el2_pkg::*;
    input  logic         ic_rd_en,
    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
    input  logic         ic_sel_premux_data, // Premux data sel
-   input el2_ic_data_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]         ic_data_ext_in_pkt,
-   input el2_ic_tag_ext_in_pkt_t    [pt.ICACHE_NUM_WAYS-1:0]           ic_tag_ext_in_pkt,
 
    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
    input  logic [70:0]               ic_debug_wr_data,   // Debug wr cache.

diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv
@@ -389,10 +389,6 @@ import el2_pkg::*;
 
    // ICache export interface
    el2_mem_if.veer_icache_src              el2_icache_export,
- // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not)
-
-   input                                   el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
-   input                                   el2_ic_tag_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
 
    input logic                             timer_int,
    input logic                             soft_int,

diff --git a/design/ifu/el2_ifu_ic_mem.sv b/design/ifu/el2_ifu_ic_mem.sv
@@ -51,8 +51,6 @@ import el2_pkg::*;
       input logic [pt.ICACHE_NUM_WAYS-1:0]          ic_tag_valid,       // Valid from the I$ tag valid outside (in flops).
 
       el2_mem_if.veer_icache_src icache_export,
-      input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
-      input el2_ic_tag_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0]                          ic_tag_ext_in_pkt,    // this is being driven by the top level for soc testing/etc
 
       output logic [pt.ICACHE_NUM_WAYS-1:0]         ic_rd_hit,          // ic_rd_hit[3:0]
       output logic                                  ic_tag_perr,        // Tag Parity error
@@ -143,7 +141,6 @@ import el2_pkg::*;
 
       input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit,
       el2_mem_if.veer_icache_data         icache_export,
-      input el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,   // this is being driven by the top level for soc testing/etc
       // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
       /*verilator coverage_off*/
       input  logic                         scan_mode
@@ -746,7 +743,6 @@ import el2_pkg::*;
       input logic [pt.ICACHE_NUM_WAYS-1:0]                         ic_debug_way,         // Debug way. Rd or Wr.
 
       el2_mem_if.veer_icache_tag                                  icache_export,
-      input el2_ic_tag_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0]    ic_tag_ext_in_pkt,
 
       output logic [25:0]                                          ictag_debug_rd_data,
       input  logic [70:0]                                          ic_debug_wr_data,     // Debug wr cache.

diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv
@@ -1307,10 +1307,6 @@ veer_wrapper rvtop_wrapper (
     .dccm_ecc_single_error  (),
     .dccm_ecc_double_error  (),
 
-// remove mems DFT pins for opensource
-    .ic_data_ext_in_pkt     ('0),
-    .ic_tag_ext_in_pkt      ('0),
-
     .soft_int               (soft_int),
     .core_id                ('0),
     .scan_mode              ( 1'b0 ),         // To enable scan mode

diff --git a/testbench/veer_wrapper.sv b/testbench/veer_wrapper.sv
@@ -284,11 +284,6 @@ module veer_wrapper
     input  logic        dbg_bus_clk_en,  // Clock ratio b/w cpu core clk & AHB master interface
     input  logic        dma_bus_clk_en,  // Clock ratio b/w cpu core clk & AHB slave interface
 
-    // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not)
-
-    input                                   el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
-    input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
-
     input logic                      timer_int,
     input logic                      soft_int,
     input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,