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Add CI workflow for UVM testbench
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Signed-off-by: Krzysztof Bieganski <[email protected]>
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kbieganski committed Nov 9, 2023
1 parent f5a4606 commit 4a8e19d
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Showing 4 changed files with 106 additions and 6 deletions.
17 changes: 14 additions & 3 deletions .github/workflows/build-verilator.yml
Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,20 @@ jobs:
verilator:
name: Build Verilator
runs-on: ubuntu-latest
strategy:
matrix:
include:
- version: v5.010
repo: verilator/verilator
commit: v5.010
- version: uvm
repo: antmicro/verilator-1
commit: df36e9ca2597aebe4b92c72461d945745b36c3e0
env:
TOOL_NAME: verilator
TOOL_VERSION: v5.010
TOOL_VERSION: ${{ matrix.version }}
TOOL_REPO: ${{ matrix.repo }}
TOOL_COMMIT: ${{ matrix.commit }}
DEBIAN_FRONTEND: "noninteractive"

steps:
Expand Down Expand Up @@ -56,9 +67,9 @@ jobs:
run: |
export CCACHE_DIR=/opt/verilator/.cache
ccache --show-config | grep cache_dir
git clone https://github.com/verilator/verilator
git clone https://github.com/${{ env.TOOL_REPO }} verilator
pushd verilator
git checkout ${{ env.TOOL_VERSION }}
git checkout ${{ env.TOOL_COMMIT }}
autoconf
./configure --prefix=/opt/verilator
make -j `nproc`
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5 changes: 5 additions & 0 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,11 @@ jobs:
needs: [Build-Verilator, Build-Spike]
uses: ./.github/workflows/test-riscof.yml

Test-UVM:
name: Test-UVM
needs: [Build-Verilator]
uses: ./.github/workflows/test-uvm.yml

Report-Coverage:
name: Report-Coverage
needs: [Test-Regression, Test-Verification, Test-RISCV-DV, Test-RISCOF]
Expand Down
84 changes: 84 additions & 0 deletions .github/workflows/test-uvm.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,84 @@
name: VeeR-EL2 verification

on:
workflow_call:

jobs:
tests:
name: UVM tests
runs-on: ubuntu-latest
env:
CCACHE_DIR: "/opt/uvm/.cache/"
VERILATOR_VERSION: uvm
DEBIAN_FRONTEND: "noninteractive"
steps:
- name: Setup repository
uses: actions/checkout@v3
with:
submodules: recursive

- name: Setup Cache Metadata
id: cache_metadata
run: |
date=$(date +"%Y_%m_%d")
time=$(date +"%Y%m%d_%H%M%S_%N")
cache_verilator_restore_key=cache_verilator_
cache_verilator_key=${cache_verilator_restore_key}${{ env.VERILATOR_VERSION }}
cache_test_restore_key=${{ matrix.test }}_${{ matrix.coverage }}_
cache_test_key=${cache_test_restore_key}${time}
echo "date=$date" | tee -a "$GITHUB_ENV"
echo "time=$time" | tee -a "$GITHUB_ENV"
echo "cache_verilator_restore_key=$cache_verilator_restore_key" | tee -a "$GITHUB_ENV"
echo "cache_verilator_key=$cache_verilator_key" | tee -a "$GITHUB_ENV"
echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV"
echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV"
- name: Restore verilator cache
id: cache-verilator-restore
uses: actions/cache/restore@v3
with:
path: |
/opt/verilator
/opt/verilator/.cache
key: ${{ env.cache_verilator_key }}
restore-keys: ${{ env.cache_verilator_restore_key }}

- name: Setup tests cache
uses: actions/cache@v3
id: cache-test-setup
with:
path: |
${{ env.CCACHE_DIR }}
key: ${{ env.cache_test_key }}
restore-keys: ${{ env.cache_test_restore_key }}

- name: Install prerequisities
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git build-essential cpanminus ccache
sudo cpanm Bit::Vector
- name: Setup environment
run: |
echo "/opt/verilator/bin" >> $GITHUB_PATH
RV_ROOT=`pwd`
echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV
PYTHONUNBUFFERED=1
echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV
- name: Build UVM testbench
run: |
make -C testbench/uvm/mem build -j$(nproc)
- name: Run UVM testbench
run: |
make -C testbench/uvm/mem simulate | tee test.out
- name: Upload test output
if: always()
uses: actions/upload-artifact@v3
with:
name: uvm_test_output
path: test.out
6 changes: 3 additions & 3 deletions testbench/uvm/mem/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -85,14 +85,14 @@ $(SIM_DIR)/el2_lsu_dccm_mem.sv:
# -------------------------------------
# Make UVM test with Verilator
# -------------------------------------
$(SIM_DIR)/$(SIM_NAME).mk: ${UVM_ROOT} $(RV_ROOT)/snapshots/$(SNAPSHOT)/el2_param.vh $(VERILOG_SOURCES) $(wildcard hdl/*.sv)
verilate: ${UVM_ROOT} $(RV_ROOT)/snapshots/$(SNAPSHOT)/el2_param.vh $(VERILOG_SOURCES) $(wildcard hdl/*.sv)
$(VERILATOR) --cc --exe --main --timing -Mdir $(SIM_DIR) \
${COMPILE_ARGS} ${EXTRA_ARGS} \
${VERILOG_DEFINE_FILES} \
${VERILOG_SOURCES} \
${WARNING_ARGS}

$(SIM_DIR)/$(SIM_NAME): $(SIM_DIR)/$(SIM_NAME).mk
build: verilate
$(MAKE) -C $(SIM_DIR) $(BUILD_ARGS) -f $(SIM_NAME).mk

simulate: build
Expand All @@ -107,4 +107,4 @@ clean:
rm -rf $(UVM_DIR)


.PHONY: simulate clean
.PHONY: verilate build simulate clean

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