[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:287:- // clk ratio signals design/el2_veer_wrapper.sv:288:- input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:289:- input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:290:- input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:291:- input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface design/el2_veer_wrapper.sv:292:- design/el2_veer_wrapper.sv:293:- // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not) design/el2_veer_wrapper.sv:294:- design/el2_veer_wrapper.sv:295:- input el2_dccm_ext_in_pkt_t [pt.DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, design/el2_veer_wrapper.sv:296:- input el2_ccm_ext_in_pkt_t [pt.ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, design/el2_veer_wrapper.sv:297:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, design/el2_veer_wrapper.sv:298:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, design/el2_veer_wrapper.sv:299:- design/el2_veer_wrapper.sv:300:- input logic timer_int, design/el2_veer_wrapper.sv:301:- input logic soft_int, design/el2_veer_wrapper.sv:302:- input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, design/el2_veer_wrapper.sv:303:- design/el2_veer_wrapper.sv:304:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc design/el2_veer_wrapper.sv:305:- output logic dec_tlu_perfcnt1, design/el2_veer_wrapper.sv:306:- output logic dec_tlu_perfcnt2, design/el2_veer_wrapper.sv:307:- output logic dec_tlu_perfcnt3, design/el2_veer_wrapper.sv:308:- design/el2_veer_wrapper.sv:309:- // ports added by the soc team design/el2_veer_wrapper.sv:310:- input logic jtag_tck, // JTAG clk design/el2_veer_wrapper.sv:311:- input logic jtag_tms, // JTAG TMS design/el2_veer_wrapper.sv:312:- input logic jtag_tdi, // JTAG tdi design/el2_veer_wrapper.sv:313:- input logic jtag_trst_n, // JTAG Reset design/el2_veer_wrapper.sv:314:- output logic jtag_tdo, // JTAG TDO design/el2_veer_wrapper.sv:315:- design/el2_veer_wrapper.sv:316:- input logic [31:4] core_id, design/el2_veer_wrapper.sv:317:- design/el2_veer_wrapper.sv:318:- // external MPC halt/run interface design/el2_veer_wrapper.sv:319:- input logic mpc_debug_halt_req, // Async halt request design/el2_veer_wrapper.sv:320:- input logic mpc_debug_run_req, // Async run request design/el2_veer_wrapper.sv:321:- input logic mpc_reset_run_req, // Run/halt after reset design/el2_veer_wrapper.sv:322:- output logic mpc_debug_halt_ack, // Halt ack design/el2_veer_wrapper.sv:323:- output logic mpc_debug_run_ack, // Run ack design/el2_veer_wrapper.sv:324:- output logic debug_brkpt_status, // debug breakpoint design/el2_veer_wrapper.sv:325:- design/el2_veer_wrapper.sv:326:- input logic i_cpu_halt_req, // Async halt req to CPU design/el2_veer_wrapper.sv:327:- output logic o_cpu_halt_ack, // core response to halt design/el2_veer_wrapper.sv:328:- output l

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:344:- logic active_l2clk; design/el2_veer_wrapper.sv:345:- logic free_l2clk; design/el2_veer_wrapper.sv:343:+ logic active_l2clk; design/el2_veer_wrapper.sv:344:+ logic free_l2clk;