Only have one shared Reset tx

bittide · Dec 12, 2024 · 289ff2f · 289ff2f
1 parent 1efc421
commit 289ff2f
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Showing 4 changed files with 20 additions and 32 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
@@ -240,33 +240,29 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
         , clockPaths = takeI clockPaths
         , rxNs
         , rxPs
-        , txDatas = txCounters
+        , txDatas = repeat txCounter
         , txReadys = txAllStables
         , rxReadys = repeat (pure True)
         }
   txAllStables = repeat txAllStable
   txAllStable = xpmCdcSingle sysClk transceivers.txClock allStable1
   allStable1 = sticky sysClk syncRst allStable0
-  txResets2 =
-    map
-      (orReset (unsafeFromActiveLow txAllStable))
-      transceivers.txResets
+  txReset2 = orReset (unsafeFromActiveLow txAllStable) transceivers.txReset
 
-  txCounters = map (txCounter transceivers.txClock) txResets2
-  txCounter txClk txRst = result
+  txCounter = counter transceivers.txClock txReset2
+  counter txClk txRst = result
    where
     result = register txClk txRst enableGen (0xaabbccddeeff1234 :: BitVector 64) (result + 1)
   -- see NOTE [magic start values]
 
   -- rxFifos :: Vec LinkCount (_, _, _, _, _Signal GthRx (Maybe (BitVector 64)))
   rxFifos =
-    zipWith3
-      (go transceivers.txClock)
+    zipWith
+      (go transceivers.txClock txReset2)
       transceivers.rxClocks
-      txResets2
       transceivers.rxDatas
    where
-    go rClk wClk rRst =
+    go rClk rRst wClk =
       resettableXilinxElasticBuffer @FifoSize @_ @_ @(Maybe (BitVector 64)) rClk wClk rRst
 
   (fillLvls, fifoUnderflowsTx, fifoOverflowsTx, _ebMode, rxCntrs) = unzip5 rxFifos
@@ -278,9 +274,8 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
 
   ugns :: Vec LinkCount (Signal GthTx (BitVector 64))
   ugns =
-    zipWith
-      (-)
-      txCounters
+    map
+      (txCounter -)
       (map (fmap (fromMaybe 0x1122334411223344)) rxCntrs)
   -- see NOTE [magic start values]
 
@@ -292,7 +287,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
   -- If you see 0x99999999.......... and it's counting up, then you're receiving Nothing,
   -- but your counter is running.
 
-  ugnStable1sec = zipWith (stableForMs (SNat @1000) transceivers.txClock) transceivers.txResets ugns
+  ugnStable1sec = map (stableForMs (SNat @1000) transceivers.txClock transceivers.txReset) ugns
 
   freeUgnDatas = zipWith4 (go transceivers.txClock) (repeat sysClk) ugns fillLvls ugnStable1sec
    where

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/LinkConfiguration.hs b/bittide-instances/src/Bittide/Instances/Hitl/LinkConfiguration.hs
@@ -177,18 +177,17 @@ transceiversStartAndObserve refClk sysClk rst myIndex rxNs rxPs miso =
         , clockPaths
         , rxNs
         , rxPs
-        , txDatas = myIndexTxN
+        , txDatas = repeat myIndexTx
         , rxReadys = repeat $ pure True
         , txReadys = repeat $ pure True
         }
 
   -- synchronizes the FPGA's stable index to the individual TX clock
   -- domains of the transceivers
-  myIndexTxN =
-    fmap (zeroExtend . pack . fromMaybe 0)
-      <$> map
-        (xpmCdcStable sysClk myIndex transceivers.txClock)
-        transceivers.txResets
+  myIndexTx =
+    fmap
+      (zeroExtend . pack . fromMaybe 0)
+      (xpmCdcStable sysClk myIndex transceivers.txClock transceivers.txReset)
 
   -- check that all the received data matches with our expectations
   success =

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs b/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs
@@ -60,9 +60,8 @@ counter ::
   (KnownDomain dom) =>
   Clock dom ->
   Reset dom ->
-  Signal dom Bool ->
   Signal dom (BitVector 64)
-counter clk rst ena = let c = register clk rst (toEnable ena) counterStart (c + 1) in c
+counter clk rst = let c = register clk rst enableGen counterStart (c + 1) in c
 
 {- | Expect a counter starting at 'counterStart' and incrementing by one on each
 cycle.
@@ -133,12 +132,7 @@ goTransceiversUpTest fpgaIndex refClk sysClk rst rxNs rxPs miso =
   -- Transceiver setup
   gthAllReset = unsafeFromActiveLow spiDone
 
-  -- Send counters
-  counters =
-    zipWith
-      (counter transceivers.txClock)
-      transceivers.txResets
-      transceivers.txSamplings
+  txCounter = counter transceivers.txClock transceivers.txReset
 
   expectCounterError =
     zipWith3
@@ -170,7 +164,7 @@ goTransceiversUpTest fpgaIndex refClk sysClk rst rxNs rxPs miso =
         , clockPaths
         , rxNs
         , rxPs
-        , txDatas = counters
+        , txDatas = repeat txCounter
         , txReadys = repeat (pure True)
         , rxReadys = repeat (pure True)
         }

diff --git a/bittide/src/Bittide/Transceiver.hs b/bittide/src/Bittide/Transceiver.hs
@@ -172,7 +172,7 @@ types say otherwise.
 data Outputs n tx rx txS free = Outputs
   { txClock :: Clock tx
   -- ^ Single transmit clock, shared by all links
-  , txResets :: Vec n (Reset tx)
+  , txReset :: Reset tx
   -- ^ See 'Output.txReset'
   , txReadys :: Vec n (Signal tx Bool)
   -- ^ See 'Output.txReady'
@@ -322,7 +322,7 @@ transceiverPrbsN opts inputs@Inputs{clock, reset, refClock} =
   Outputs
     { -- tx
       txClock = txClock
-    , txResets = map (.txReset) outputs
+    , txReset = fold orReset $ map (.txReset) outputs
     , txReadys = map (.txReady) outputs
     , txSamplings = map (.txSampling) outputs
     , -- rx