More debug signals

bittide · Dec 12, 2024 · 1efc421 · 1efc421
1 parent 2aec356
commit 1efc421
Showing 1 changed file with 7 additions and 1 deletion.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs b/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs
@@ -252,6 +252,9 @@ transceiversUpTest refClkDiff sysClkDiff syncIn rxns rxps miso =
             :> "probe_failAfterUpSticky"
             :> "probe_anyErrors"
             :> "probe_expectCounterError"
+            :> "probe_sysRst"
+            :> "probe_startTest"
+            :> "probe_syncInRst"
             :> Nil
         )
           { depth = D16384
@@ -268,8 +271,11 @@ transceiversUpTest refClkDiff sysClkDiff syncIn rxns rxps miso =
         failAfterUpSticky
         anyErrors
         expectCounterErrorSys
+        (unsafeToActiveHigh sysRst)
+        startTest
+        (unsafeToActiveHigh syncInRst)
 
-  capture = anyChange sysClk sysRst $ bundle (linkUps, allUp, failAfterUp, failAfterUpSticky, anyErrors)
+  capture = anyChange sysClk sysRst $ bundle (linkUps, allUp, failAfterUp, failAfterUpSticky, anyErrors, expectCounterErrorSys,unsafeToActiveHigh sysRst,startTest,unsafeToActiveHigh syncInRst)
   timeSucc = countSucc @(Unsigned 16, Index (PeriodToCycles Basic125 (Milliseconds 1)))
   timer = register sysClk sysRst enableGen (0, 0) (timeSucc <$> timer)
   milliseconds1 = fst <$> timer