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fix(CMSIS): Match clock/trim settings in SYS registers to latest changes for MAX32657 #1183

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merged 4 commits into from
Oct 9, 2024
Merged

fix(CMSIS): Match clock/trim settings in SYS registers to latest changes for MAX32657 #1183

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fd2fff0
Update oscillator trim settings
sihyung-maxim Sep 19, 2024
0464793
Update MCR ERFO settings
sihyung-maxim Sep 26, 2024
7cd1d2a
Fix BLE registers
sihyung-maxim Oct 2, 2024
e0cbf48
Merge branch 'main' into feat/me30_fcr
sihyung-maxim Oct 2, 2024
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20 changes: 19 additions & 1 deletion Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ typedef struct {
__IO uint32_t erfoks; /**< <tt>\b 0x18:</tt> FCR ERFOKS Register */
__IO uint32_t intfl; /**< <tt>\b 0x1C:</tt> FCR INTFL Register */
__IO uint32_t inten; /**< <tt>\b 0x20:</tt> FCR INTEN Register */
__R uint32_t rsv_0x24;
__IO uint32_t erfoctrl; /**< <tt>\b 0x24:</tt> FCR ERFOCTRL Register */
__IO uint32_t frqcntctrl; /**< <tt>\b 0x28:</tt> FCR FRQCNTCTRL Register */
__IO uint32_t frqcntcmp; /**< <tt>\b 0x2C:</tt> FCR FRQCNTCMP Register */
__I uint32_t refclk; /**< <tt>\b 0x30:</tt> FCR REFCLK Register */
Expand All @@ -101,6 +101,7 @@ typedef struct {
#define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: <tt> 0x0018</tt> */
#define MXC_R_FCR_INTFL ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: <tt> 0x001C</tt> */
#define MXC_R_FCR_INTEN ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: <tt> 0x0020</tt> */
#define MXC_R_FCR_ERFOCTRL ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: <tt> 0x0024</tt> */
#define MXC_R_FCR_FRQCNTCTRL ((uint32_t)0x00000028UL) /**< Offset from FCR Base Address: <tt> 0x0028</tt> */
#define MXC_R_FCR_FRQCNTCMP ((uint32_t)0x0000002CUL) /**< Offset from FCR Base Address: <tt> 0x002C</tt> */
#define MXC_R_FCR_REFCLK ((uint32_t)0x00000030UL) /**< Offset from FCR Base Address: <tt> 0x0030</tt> */
Expand Down Expand Up @@ -236,6 +237,23 @@ typedef struct {

/**@} end of group FCR_INTEN_Register */

/**
* @ingroup fcr_registers
* @defgroup FCR_ERFOCTRL FCR_ERFOCTRL
* @brief ERFO Control Register.
* @{
*/
#define MXC_F_FCR_ERFOCTRL_CAP_X1_POS 0 /**< ERFOCTRL_CAP_X1 Position */
#define MXC_F_FCR_ERFOCTRL_CAP_X1 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X1_POS)) /**< ERFOCTRL_CAP_X1 Mask */

#define MXC_F_FCR_ERFOCTRL_CAP_X2_POS 7 /**< ERFOCTRL_CAP_X2 Position */
#define MXC_F_FCR_ERFOCTRL_CAP_X2 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X2_POS)) /**< ERFOCTRL_CAP_X2 Mask */

#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS 14 /**< ERFOCTRL_CAP_BYPASS Position */
#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS ((uint32_t)(0x1UL << MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS)) /**< ERFOCTRL_CAP_BYPASS Mask */

/**@} end of group FCR_ERFOCTRL_Register */

/**
* @ingroup fcr_registers
* @defgroup FCR_FRQCNTCTRL FCR_FRQCNTCTRL
Expand Down
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