Wider range of PLL usage #117
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I experimentally tested the PLL range to be from 30-948 MHz and it doesn't lock when fpfd = 2 MHz and fvco = 600 MHz but it does when fvco = 300 MHz or smaller. For example CLKOP_DIV=1 CLKFB_DIV=25 CLKI_DIV=6 works while CLKOP_DIV=12 CLKFB_DIV=25 CLKI_DIV=6 does not. Signed-off-by: x44203 <[email protected]>
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The user should probably be warned if operating outside of the officially supported specs. Something non-obvious could be broken ... |
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@smunaut is definitely right here. I've also got no idea why you think one experiment, presumably on one device at one voltage and temperature, is more useful than a tested and guaranteed datasheet spec that Diamond also uses. |
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I experimentally tested the PLL range to be from 30-948 MHz and it doesn't lock when fpfd = 2 MHz and fvco = 600 MHz but it does when fvco = 300 MHz or smaller. For example CLKOP_DIV=1 CLKFB_DIV=25 CLKI_DIV=6 works while CLKOP_DIV=12 CLKFB_DIV=25 CLKI_DIV=6 does not.