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I experimentally tested the PLL range to be from 30-948 MHz and it doesn't lock when fpfd = 2 MHz and fvco = 600 MHz but it does when fvco = 300 MHz or smaller. For example CLKOP_DIV=1 CLKFB_DIV=25 CLKI_DIV=6 works while CLKOP_DIV=12 CLKFB_DIV=25 CLKI_DIV=6 does not.
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