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Apple IIgs Memory Map
The Apple IIgs has a 24-bit address space, which is conventionally broken down into 256 banks of 64kb.
The final 16 banks are set aside for up to one megabyte of ROM.
The built-in ROMs for the IIgs were initially 128kb, and later 256kb. In both cases they fill the end of the ROM area.
ROM access is always 'fast' — access windows are five cycles of the 14Mhz clock.
Banks $E0 and $E1 access memory via the IIe-emulating Mega II chip. Bank $E0 contains main RAM and bank $E1 contains auxiliary RAM. They are subject to language-card banking only.
The video buffer always lives in this area.
Both reads and writes are performed via the Mega II so are 'slow' — access windows are fourteen cycles of the 14Mhz clock, with one exception: every 64th window is sixteen cycles.
The extended 64th window ensures that video remains in phase with the NTSC colour subcarrier.
Banks $02–$7f contain regular system RAM and are not subject to paging or other rearrangement.
RAM access is 'fast' — windows are five cycles of the 14Mhz clock, though one window in ten is lost to memory refresh.
The first 128kb of fast RAM occupies banks $00 and $01.
Language card banking affects both banks; other auxiliary/main selections may expose parts of bank $01 within bank $00.
Parts of these banks may additionally be shadowed to corresponding regions of $e0 and $e1. Auxiliary paging is applied before shadowing, so a write to bank $00 that is redirected to $01 will be shadowed to $e1.
Bit 4 of the speed register can enable shadowing in all banks, based only upon address line 16. Shadowing will otherwise apply in banks $00 and $01 only.
Orthogonally, bit 0 of the new video register permits address line 16 to be blocked for shadowing. In that case all shadowed writes will be directed to bank $e0.
The 65816's VPB (i.e. vector pull) signal always selects the final bank of ROM.