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The Enterprise
The Enterprise is a late-generation Z80-based computer with custom audio and video chips.
Nick is the Enterprise's video chip, offering text and pixel modes at up to 8 bits per pixel output; it uses a line parameter table potentially to obtain a unique mode and palette for every line of the display. Unusually for a computer of the period, it runs asynchronously from the processor.
Nick provides 57 slots per line, each slot being 16 cycles wide, for a total of 912 cycles/line. In its highest resolution mode it can output one pixel per cycle.
It is stated to be 'phaselocked' with the PAL colour subcarrier on PAL machines — in context this appears to means in-phase rather than e.g. subject to a PLL. Two possible timings to achieve this are floated in the preproduction documentation.
Taking that to mean that 912 cycles equates to a slightly-overlong line of exactly 284 colour cycles:
- each line should last 284*64/283.7516 µs = 45440000/709379 µs ≈ 64.06µs;
- therefore there are 1000000 / (45440000/709379) = 709379000000/45440000 = 17734475/1136 ≈ 15611.33 lines/second;
- which implies an ideal clock rate of 912*17734475/1136 = 1010865075/71 Hz ≈ 14,237,536.27 Hz.
That gives (1010865075/71) / 4000000 = 1010865075/284000000 = 40434603/11360000 ≈ 3.56 Nick cycles for every Z80 cycle.
Nick is fed with a clock rate of exactly 1/5th the PAL colour subcarrier, which drives eight separate out-of-phase internal clocks, to produce a pixel clock at 16/5ths the PAL colour subcarrier.
That would imply a pixel clock of 16/5 * 4.43361875Mhz = 14,187,580 Hz.
A 912-cycle line would then take 912/14187580 = 228/3546895 ≈ 64.28 µs; relative to the subcarrier, each would be 912*5/16 = 285 colour cycles long.
Per its documentation, EP128Emu prefers the former, or close enough, providing a table of built-in clock rates that "assume 14237536 Hz as the NICK frequency".
Nick marshals 64kb of memory; if the Z80 wants to access that 64kb or to access one of Nick's registers then it must wait for an access window.
Each 16-cycle Nick slot is divided as:
- five cycles for a first VRAM read;
- five cycles for a second VRAM read; and
- six cycles for a Z80 access.
The Z80's clock will be paused in order to align its access with the available window; the clock can be held only in multiples of a half cycle.
Since six Nick cycles are around 1.69 Z80 cycles, meaning that in the first case just less than 1.19 Z80 cycles will be available after waiting for a half-cycle to begin, I assume this means that the final cycle of any affected Z80 bus cycle is held until the first half-cycle that is wholly inside an access window.
Dave is the Enterprise's audio and IO chip, providing three tone channels and one noise, along with high-pass filtering and ring modulation. It is also responsible for interrupt status, and manipulations of the memory map.
Dave uses a four-entry table to map the top 2 bits of the Z80's 16-bit address bus to 8 bits, producing a total address space of 22 bits, i.e. 4 megabytes, pageable in 16kb chunks.
Specifically it provides four read/write registers at ports B0–B3, representing the 16kb region to map in the Z80's [0000, 3FFF], [4000, 7FFF], [8000, BFFF] and [C000, FFFF] regions.
The unexpanded 64kb machine divides this up as:
- Banks 0 and 1: the built-in EXOS ROM; and
- Banks FC–FF: the 64kb of RAM shared with Nick.
The 128kb machine adds a further four banks of RAM at F8–FB; further expansion RAM usually populates the 4mb address space downward from there.
At reset all four paging registers are cleared to 0, making the first 16kb of the EXOS ROM visible in all four segments of the Z80's addressing space.
IstvánV provides detailed Hungarian notes here. The following is a result of machine translating those via a couple of different online translators and synthesising the results.
Four polynomial counters are implemented.
The smallest three are 4, 5 and 7 bits in length. These three run continuously at 250 kHz. They may be sampled by the tone generators.
The fourth is of variable length, being configurable to either 9, 11, 15 or 17 bits in length. It is clocked according to the configuration of the noise channel.
The programmer can opt to provide the noise channel's polynomial counter the tone generators, replacing the 7 bit counter.
Polynomials in use are:
- 0xc
- 0x14
- 0x60
- 0x110
- 0x500
- 0x6000
- 0x12000
i.e. a potential C-style implementation is:
output = counter & 1;
counter = (counter >> 1) ^ (output ? polynomial_as_listed : 0);
Each channel has a flip flop specifying its current state — high or low.
Standard operation: a 12-bit counter counts downwards from the specified reload value at a rate of 250 kHz (on a 4 Mhz machine, if bit 1 of port BFh is clear). It is reloaded when it overflows, and:
- if no distortion is specified, the output switches state;
- otherwise the specified polynomial output is sampled and becomes the generator's new state.
If high-pass filtering is enabled, any falling edge on the linked channel's output resets this channel's state.
If ring modulation is enabled, the channel's actual output is the XNOR of its output and that of the other channel.
In both cases, the other channel's output is that after the application of distortion, high-pass filtering and ring modulation.
The order of operations is:
- update square wave;
- apply the high-pass filter;
- apply ring modulation.
This clocks its own polynomial counter, selectably either 9, 11, 15 or 17 bits in length. It will advance each time it observes a falling edge on its input.
It is clocked at the programmed rate, being any of:
- 31.25 kHz, i.e. upon every falling clock of the 250 kHz clock, divided by four; or
- upon the falling edge of any tone channel's output (i.e. after distortion, high-pass filtering and ring modulation).
The optional high-pass filter and ring modulator work as they do for the tone channels.
If the low-pass filter is enabled then falling edges of the noise generator's state sample output channel 2 in order to generate the noise output.
The order of operations is:
- update polynomial;
- apply the low-pass filter;
- apply the high-pass filter;
- apply ring modulation.
This isn't covered overtly but the documentation makes reference to time-division multiplexing for channel output; a guess might therefore be that channels are merely updated sequentially, with reference to the most recent prior output of other channels to which they refer.