Merge pull request #44 from cyprienh/vga_linux

Ajout du VGA et de Linux

.gitignore

@@ -8,7 +8,7 @@ transcript
 .moore
 *.vstf
 wlft*
-*nfs*
+#*nfs*
 src/moore.sv
 *.sig
 *.dtb
@@ -23,16 +23,32 @@ build/
 *.out
 *.jou
 *.o
-uart
+*.xci
+*.pb
+*.rpt
+*.bin
+*.D
+*.hex
+*.mem
+*.xpr
+*.a
+*.coe
+*.riscv
+#uart
 work-ver/*
 corev_apu/fpga/work-fpga
 corev_apu/fpga/reports/
 corev_apu/fpga/scripts/add_sources.tcl
-corev_apu/fpga/ariane.xpr
+corev_apu/fpga/cva6_fpga.xpr
 corev_apu/fpga/ariane.cache/
 corev_apu/fpga/ariane.hw/
 corev_apu/fpga/.Xil/
 corev_apu/fpga/mode*
+corev_apu/fpga/*.runs/
+corev_apu/fpga/*.cache/
+corev_apu/fpga/*.hw/
+corev_apu/fpga/*.srcs/
+corev_apu/fpga/reports_*/
 stdout/
 work-dpi/
 tb/riscv-isa-sim/

.gitmodules

@@ -40,3 +40,15 @@
 [submodule "core/cache_subsystem/hpdcache"]
 	path = core/cache_subsystem/hpdcache
 	url = https://github.com/openhwgroup/cv-hpdcache.git
+[submodule "cva6-sdk/buildroot"]
+	path = cva6-sdk/buildroot
+	url = git://git.buildroot.net/buildroot
+[submodule "cva6-sdk/riscv-isa-sim"]
+	path = cva6-sdk/riscv-isa-sim
+	url = https://github.com/riscv/riscv-isa-sim.git
+[submodule "cva6-sdk/riscv-tests"]
+	path = cva6-sdk/riscv-tests
+	url = https://github.com/riscv/riscv-tests.git
+[submodule "cva6-sdk/vitetris"]
+	path = cva6-sdk/vitetris
+	url = https://github.com/pulp-platform/vitetris.git

Makefile

@@ -131,7 +131,8 @@ ariane_pkg := \
               corev_apu/register_interface/src/reg_intf.sv           \
               corev_apu/tb/ariane_soc_pkg.sv                         \
               corev_apu/riscv-dbg/src/dm_pkg.sv                      \
-              corev_apu/tb/ariane_axi_soc_pkg.sv
+              corev_apu/tb/ariane_axi_soc_pkg.sv                     \
+              corev_apu/fpga/src/axi_vga/src/axi_vga_reg_pkg.sv
 ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
 
 # Test packages
@@ -175,6 +176,8 @@ src :=  core/include/$(target)_config_pkg.sv
         $(wildcard corev_apu/fpga/src/axi_slice/src/*.sv)                            \
         $(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv)                         \
         $(wildcard corev_apu/axi_mem_if/src/*.sv)                                    \
+        $(wildcard corev_apu/fpga/src/axi_vga/src/*.sv)                              \
+        corev_apu/fpga/src/axi_vga/src/afifo.v                                       \
         corev_apu/rv_plic/rtl/rv_plic_target.sv                                      \
         corev_apu/rv_plic/rtl/rv_plic_gateway.sv                                     \
         corev_apu/rv_plic/rtl/plic_regmap.sv                                         \
@@ -192,7 +195,7 @@ src :=  core/include/$(target)_config_pkg.sv
         vendor/pulp-platform/common_cells/src/rstgen_bypass.sv                       \
         vendor/pulp-platform/common_cells/src/rstgen.sv                              \
         vendor/pulp-platform/common_cells/src/addr_decode.sv                         \
-	vendor/pulp-platform/common_cells/src/stream_register.sv                     \
+        vendor/pulp-platform/common_cells/src/stream_register.sv                     \
         vendor/pulp-platform/axi/src/axi_cut.sv                                      \
         vendor/pulp-platform/axi/src/axi_join.sv                                     \
         vendor/pulp-platform/axi/src/axi_delayer.sv                                  \
@@ -210,6 +213,16 @@ src :=  core/include/$(target)_config_pkg.sv
         vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv                  \
         vendor/pulp-platform/common_cells/src/stream_delay.sv                        \
         vendor/pulp-platform/common_cells/src/lfsr_16bit.sv                          \
+		vendor/pulp-platform/common_cells/src/fifo_v3.sv                             \
+        vendor/pulp-platform/common_cells/src/stream_join.sv                         \
+        vendor/pulp-platform/common_cells/src/stream_fifo.sv                         \
+        vendor/pulp-platform/common_cells/src/onehot_to_bin.sv                       \
+        vendor/pulp-platform/common_cells/src/lzc.sv                                 \
+        vendor/pulp-platform/common_cells/src/id_queue.sv                            \
+        vendor/pulp-platform/axi/src/axi_burst_splitter.sv                           \
+        corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv \
+        corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv \
+        corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg.sv     \
         vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv  \
         vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv     \
         vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv                    \
@@ -342,7 +355,7 @@ sim: build
 	echo $(riscv-benchmarks)
 	vsim${questa_version} +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
 	 $(uvm-flags) $(QUESTASIM_FLAGS)  \
-	${top_level}_optimized +permissive-off +binary_mem=$(APP_PATH)/$(APP).mem | tee sim.log
+	${top_level}_optimized +permissive-off +binary_mem=fw_payload.mem | tee sim.log
 
 
 run-benchmarks: $(riscv-benchmarks)
@@ -676,6 +689,10 @@ program_cva6_fpga:
 	@echo "[FPGA] Program FPGA"
 	cd corev_apu/fpga && make program_cva6_fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS) BATCH_MODE=$(BATCH_MODE)
 
+sdk:
+	@echo "[FPGA] Building Linux using Buildroot"
+	cd cva6-sdk && make images
+
 
 build-spike:
 	cd tb/riscv-isa-sim && mkdir -p build && cd build && ../configure --prefix=`pwd`/../install --with-fesvr=$(RISCV) --enable-commitlog && make -j8 install

README.md

@@ -6,8 +6,9 @@ https://cva6.readthedocs.io/en/latest/
 
 Checkout the repository and initialize all submodules:
 ```
-$ git clone https://github.com/ThalesGroup/cva6-softcore-contest.git
-$ git submodule update --init --recursive
+git clone https://github.com/ThalesGroup/cva6-softcore-contest.git
+git checkout vga_linux
+git submodule update --init --recursive
 ```
 
 Do not forget to check all the details of the contest in [Annonce RISC-V contest 2023-2024 v2.pdf](./Annonce%20RISC-V%20contest%202023-2024%20v2.pdf).
@@ -66,12 +67,12 @@ In our case, we use this cable to program software applications on the CV32A6 in
 
 2. Generate the bitstream of the FPGA platform:
 ```
-$ make cva6_fpga
+make cva6_fpga_ddr
 ```
 
 3. When the bitstream is generated, switch on Zybo board and run:
 ```
-$ make program_cva6_fpga
+make program_cva6_fpga
 ```
 When the bitstream is loaded, the green LED `done` lights up.
 ![alt text](./docs/pictures/20201204_160542.jpg)
@@ -80,6 +81,58 @@ When the bitstream is loaded, the green LED `done` lights up.
 
 Now, the hardware is ready and the hyperterminal is connected to the UART output of the FPGA. We can now start the software.
 
+## Build and boot Linux on the FPGA
+
+To use Linux, you need to generate the bitstream using:
+```
+make cva6_fpga_ddr
+```
+
+### Building Linux
+
+This project uses Buildroot to build a small Linux image that can be run on CVA6. Several steps are needed before booting Linux. OpenSBI and U-Boot are used to interface with the CVA6 platform and provide needed functions to Linux. The `cva6-sdk` folder contains everything that is needed. To build the images, run:
+```
+make sdk
+```
+If you want to add files to Linux' file system, you can simply add them to the `cva6-sdk/rootfs/` folder.
+
+### Running Linux on Zybo
+
+To run Linux on the Zybo FPGA, you will need a RISC-V version of GDB, if you don't already have it, a version is compiled by Buildroot when you build the Linux image. You can find it at `cva6-sdk/buildroot/output/host/bin/riscv32-buildroot-linux-gnu-gdb`.
+Flash the bitstream as explained previously and then run the following command from the root of the project:
+```
+openocd -f corev_apu/fpga/cva6.cfg
+```
+If it produces error, try resetting CVA6 by clicking `BTN3` of the board.
+In a separate terminal, go to the `cva6-sdk/install32` folder and run the following command:
+```
+/path/to//riscv32-buildroot-linux-gnu-gdb fw_payload.elf
+```
+This will start GDB from which you will have to run the following commands:
+```
+tar ext :3333
+restore uImage binary 0x90000000
+load
+set $a0=0
+set $a1=0x11200
+c
+```
+These commands copy the images in CVA6's memory and setup the needed arguments to start the boot sequence.
+The `c` command will start the execution of the different programs starting with OpenOCD, the U-Boot and finally Linux, all is automated and should take about 2-3 minutes to get inside Linux.
+
+### Setting up the VGA link
+
+Plug the PmodVGA dongle into the `JC` and `JD` Pmod connectors of the Zybo board (between the HS2 and the serial adapters).
+In Linux, run the following commands:
+```
+dd if=/dev/zero of=/dev/fb0 count=1200
+devmem 0x50000000 8 0x1
+export SDL_VIDEODRIVER=dummy
+chocolate-doom
+``` 
+This will start Doom running on the VGA display. There are other test programs to play with the VGA display such as the `fb-test-*` suite or `fbv`.
+Have fun!
+
 ## Get started with software environment
 
 ### Building the docker image

core/Flist.cva6

@@ -92,6 +92,17 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/unread.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/popcount.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/exp_backoff.sv
 
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_join.sv 
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/stream_fifo.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/onehot_to_bin.sv 
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lzc.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/id_queue.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_burst_splitter.sv
+${CVA6_REPO_DIR}/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv
+${CVA6_REPO_DIR}/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv
+${CVA6_REPO_DIR}/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv
+${CVA6_REPO_DIR}/corev_apu/register_interface/vendor/lowrisc_opentitan/src/prim_subreg.sv
+
 // Common Cells for example coprocessor
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/counter.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/delta_counter.sv

corev_apu/fpga/constraints/cva6_fpga.xdc

@@ -19,4 +19,3 @@ set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_ds
 set_multicycle_path -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 4
 set_multicycle_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 3
 
-

corev_apu/fpga/constraints/zybo_z7_20.xdc

@@ -15,8 +15,24 @@ set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports tms]
 set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports tx]
 set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports rx]
 
-
-
+## VGA
+## PMOD Header JC
+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {red[0]}]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {red[1]}]
+set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {red[2]}]
+set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {red[3]}]
+set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports {blue[0]}]
+set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports {blue[1]}]
+set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports {blue[2]}]
+set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {blue[3]}]
+
+## PMOD Header JD
+set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {green[0]}]
+set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {green[1]}]
+set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {green[2]}]
+set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {green[3]}]
+set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports hsync]
+set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports vsync]
 
 ## JTAG
 # minimize routing delay
@@ -30,3 +46,11 @@ set_max_delay -from [get_ports trst_n] 20.000
 set_false_path -from [get_ports trst_n]
 
 
+
+
+
+
+
+
+
+

corev_apu/fpga/cva6.cfg

@@ -0,0 +1,35 @@
+adapter speed     1000
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6014
+
+ftdi channel 0
+ftdi layout_init 0x00e8 0x60eb
+# ftdi layout_init 0x0018 0x001b
+ftdi layout_signal nTRST -ndata 0x0010
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
+
+riscv set_mem_access progbuf sysbus abstract
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+riscv resume_order reversed
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+
+# prefer to use sba for system bus access
+# riscv set_prefer_sba off
+
+scan_chain
+bindto 0.0.0.0
+
+init
+halt
+echo "Ready for Remote Connections"