v6.0.14

Commits

• e2c4806: fix config (qarlosalberto) #696

What's Changed

• Expose commands by @qarlosalberto in #694
• fix config by @qarlosalberto in #696

Full Changelog: v6.0.13...v6.0.14

v6.0.13

Features

• cheek tools #686 (qarlosalberto)
• check tools vsg #686 (qarlosalberto)
• add links to doc #686 (qarlosalberto)

Bug Fixes

• update eslint config #686 (qarlosalberto)

Commits

• 6ec4ba1: add docLink to config (qarlosalberto) #686
• 09d369e: automatic release notes version (qarlosalberto) #686

v6.0.12

What's Changed

• feat: run yowasp-yosys from output dir by @qarlosalberto in #675
• feat: better config view by @qarlosalberto in #681
• Fix ls stop by @qarlosalberto in #684

Full Changelog: v6.0.9...v6.0.12

v6.0.9

Features

• use path for base view
• mix vhdl and verilog/sv schematic

v6.0.4

• 1st class support for Intel@ Quartus@ Prime Pr
• Individual project configuration.
• New tool added: SandPiper™.
• Support for TL-Verilog.
• Bug fixing.

v5.0.11

Bug Fixes

• save project with relative paths (qarlosalberto)

v5.0.10

chore: ci test for json2yaml

v5.0.8

Bug Fixes

• documenter with tables (qarlosalberto)

v5.0.7

Features

• add alert when schematic graph exceeds the maximum size (qarlosalberto)

Chores

• update doc links (qarlosalberto)

v5.0.6

Features

• improve linter/formater path detection (qarlosalberto)

Bug Fixes

• component vhdl template (qarlosalberto)

Chores

• release notes (qarlosalberto)