0.23.0

Updates:

• Add preprocessor ifndef SYNTHESIS guard around RTL assertions to avoid synthesis warnings. #104
• Fix incorrect bit-order of external register packed struct fields. #111
• Add optional dependency that includes peakrdl-cli by installing via peakrdl-regblock[cli]. Allows for lightweight PeakRDL tool install option.
• Add next_q storage element to reset clause to avoid synthesis issues with async resets. #113, #89
• Fix incorrect address width calculation for external block address assignment. #116
• Remove excessive secondary counter saturation clamping logic. Counters will now be allowed to be loaded with values beyond their saturation point if loaded through non-increment/decrement mechanisms. #114
• Add width cast to address decode loop iterators. #92

0.22.0

Updates:

• Add support for CPUIFs to provide parameters to the module #80
• Add packed struct overlay for external register bitfields. #84
• Use explicit logic type for user enum declarations. #91

0.21.0

Updates:

• Remove use of in-scope initial assignments to automatics to work around bug in Spyglass lint tool. #87
• Fix read/write buffering trigger generation when trigger is not the same reg. #88

0.20.0

Updates:

• Fix invalid bit-slicing of literals if field reset value is a constant. #71
• Add validation check for write buffered registers that trigger off of their own field. #39
• Fix accidental blocking assignment in always_ff for read buffering storage elements.
• Tidy up some whitespace.

0.19.0

Updates:

• Fix hwif type name generation to properly include parameterized component type names. #70
• Remove implication operator to avoid xsim compatibility limitation. #57
• Fix always_ff generation for non-reset fields and async default reset. #63
• Fix axi4-lite write strobe width. #68

0.18.0

Updates:

• Add assertion for rogue external ack strobes. #57
• Omit unnecessary hwif signals if an external register is read-only or write-only. #58
• Discard LSbs of address for AXI4-Lite CPUIF to properly handle unaligned transfers. #60
• Add parameters for CPUIF data and addr widths to package output.

0.17.0

Updates:

• Fix interrupt conditional predicates to be single-bit. #54
• Clean up ugly unconditional 'if(1)' conditionals in field logic. #50

0.16.0

Updates:

• Fix oversized address width calculation edge case. #46
• Use sized integer literals in comparisons. #49
• Fix modulo-zero edge case if exporting a block that contains no internal registers. #53

0.15.0

Updates:

• Use sized integer literals if bit width exceeds 32-bits. #43

0.14.0

Updates:

• Add ability to control default reset style. #34
• Add Intel Avalon MM cpuif. #40
• Add support for field paritycheck. #35
• Fix bug where small designs with 3 or less sw readable addresses, and readback retiming enabled, generate incorrect output.