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Issues: SystemRDL/PeakRDL-regblock

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24 Open 88 Closed
24 Open 88 Closed
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Issues list

[FEATURE] support arbitrary sequence in rdl filelist with "-f" optoin to run a instantiation of rdl invalid This doesn't seem right
#132 opened Jan 3, 2025 by williammajp
1
[FEATURE] Emit error if field uses a dynamic reset value for an async reset feature request New feature or request
#129 opened Dec 20, 2024 by amykyta3
[FEATURE] Add simulation-time width assertions to SV interfaces feature request New feature or request
#128 opened Dec 20, 2024 by amykyta3
stickybit predicate causes dead code bug Something isn't working
#127 opened Dec 20, 2024 by amykyta3
Be more intelligent about creation of overflow/underflow/saturate signals feature request New feature or request
#126 opened Dec 20, 2024 by amykyta3
[cleanup] Field logic Jinja templates are starting to get messy. Refactor
#125 opened Dec 20, 2024 by amykyta3
[FEATURE] AHB interface support feature request New feature or request
#119 opened Oct 1, 2024 by Blebowski
6
[FEATURE] Parameters in regblock package feature request New feature or request
#112 opened May 24, 2024 by benoitdenkinger
More optimized readback stage RTL generation invalid This doesn't seem right wontfix This will not be worked on
#103 opened Apr 27, 2024 by Blebowski
4
Unaligned external addressable components
#101 opened Apr 23, 2024 by maltaisn
Interface data width vs register width vs access width
#100 opened Apr 18, 2024 by jscheid-ventana
1
hwset on multibit field feature request New feature or request
#99 opened Apr 16, 2024 by darrylring
5
unconditional is None # Can only have one unconditional assignment per field bug Something isn't working
#93 opened Apr 3, 2024 by xachb
2
User defined property for specifying cpuif
#77 opened Dec 14, 2023 by RasmusGOlsen
1
1
Raising an error for unauthorized read or write feature request New feature or request
#76 opened Dec 11, 2023 by imerkado91
6
During export, check for identifier collisions in output feature request New feature or request
#73 opened Nov 7, 2023 by amykyta3
VHDL Package Compatibilty feature request New feature or request
#61 opened Aug 16, 2023 by eddlestar
2
Feature Request: Option to remove buffer stage from AXI read/write feature request New feature or request
#47 opened Jun 12, 2023 by leolitenstorrent
@amykyta3
6
Verilator support
#41 opened Jun 1, 2023 by Risto97
6
Add support for write broadcasting feature request New feature or request
#37 opened Apr 12, 2023 by amykyta3
@amykyta3
Emit Parametrized PeakRDL output feature request New feature or request
#33 opened Apr 4, 2023 by galaviel
24
Add support for alias registers feature request New feature or request
#32 opened Mar 25, 2023 by amykyta3
1
Add option to generate a UVM HDL Path overlay feature request New feature or request
#15 opened Jun 23, 2022 by amykyta3
VHDL exporter feature request New feature or request
#11 opened Jun 22, 2022 by MarekPikula
4
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