Skip to content

Ridwan-Hussain/Computer-Architecture

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Computer-Architecture

Created a CPU in Verilog for ECE251 Final Project.

Rob Website

https://github.com/robmarano/cpu_hdl_catalog/tree/STEP-01

OttoBit Spreadsheet

https://cooperunion.sharepoint.com/:x:/r/sites/Section_ECE-251-A-2023SP/_layouts/15/Doc.aspx?action=edit&sourcedoc=%7B2cd312b1-8aa7-483c-a74d-31bccdc8a4b7%7D&wdOrigin=TEAMS-WEB.teamsSdk.openFilePreview&wdExp=TEAMS-CONTROL&web=1

ISA for Besties CPU

image Datapath for our CPU.

image Register, Immediate, and Address Instruction Types Formating

image The instructions we defined for R-type and how their bit values are defined.

image The instructions we defined for I-type and how their bit values are defined.

image The instructions we defined for J-type and how their bit values are defined.

  1. The ALU Operand Size is 32 bits.
  2. We'd support 12 ALU operations: add, subtract, shift left, shift right, and, or, xor, nor, nand, nor, jr, set less than, and set greater than.
  3. The Operational Code (OpCode) will be 5 bits.
  4. We'll provide 128 registers for the programs (7 bits for register addressing).
  5. We will have a return address to receive the results of the ALU ($ra, reg #127)
  6. We'll have 3 types of instruction format: Register (R), Immediate (I), & Jump (J)
  7. Our instruction width will be a fixed value of 32 bits.
  8. We'll design our datapath and Control Unit similar to MIPs but make any changes we want/need to make.
  9. The datapath and control unit will be implemented using a single-cycle instruction execution since will plan on using RISC.
  10. The single-cycle implementation won't be converted to a pipelined design.
  11. Our Verilog Components include: Adder, Alu, AluDecoder, Clock, Computer, Controller, Cpu, D-Flip Flops, Datapath, Dmem, FullAdder, Imem, MainDecoder, Mux (2:1), RegisterFile, SignExtender, and Sl2 (Shift left 2)

Other Decisions Made

  • First two bits for OpCode determine instruction type (01 or 10 for Register, 11 for Immediate, 00 for Jump)
  • We'll be storing our numbers using Little Endianness
  • Registers are written on rising edge
  • For our code, n=32 bits and r=7 bits. n is for the operand bit size and r represents the number of bits we have for our registers.

About

Created a MIPs CPU in Verilog for ECE251.

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published