Computer-Architecture

Created a CPU in Verilog for ECE251 Final Project.

Rob Website

^{Datapath for our CPU.}

^{Register, Immediate, and Address Instruction Types Formating}

^{The instructions we defined for R-type and how their bit values are defined.}

^{The instructions we defined for I-type and how their bit values are defined.}

^{The instructions we defined for J-type and how their bit values are defined.}

The ALU Operand Size is 32 bits.
We'd support 12 ALU operations: add, subtract, shift left, shift right, and, or, xor, nor, nand, nor, jr, set less than, and set greater than.
The Operational Code (OpCode) will be 5 bits.
We'll provide 128 registers for the programs (7 bits for register addressing).
We will have a return address to receive the results of the ALU ($ra, reg #127)
We'll have 3 types of instruction format: Register (R), Immediate (I), & Jump (J)
Our instruction width will be a fixed value of 32 bits.
We'll design our datapath and Control Unit similar to MIPs but make any changes we want/need to make.
The datapath and control unit will be implemented using a single-cycle instruction execution since will plan on using RISC.
The single-cycle implementation won't be converted to a pipelined design.
Our Verilog Components include: Adder, Alu, AluDecoder, Clock, Computer, Controller, Cpu, D-Flip Flops, Datapath, Dmem, FullAdder, Imem, MainDecoder, Mux (2:1), RegisterFile, SignExtender, and Sl2 (Shift left 2)

First two bits for OpCode determine instruction type (01 or 10 for Register, 11 for Immediate, 00 for Jump)
We'll be storing our numbers using Little Endianness
Registers are written on rising edge
For our code, n=32 bits and r=7 bits. n is for the operand bit size and r represents the number of bits we have for our registers.