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7 followers · 17 following
  • Gampaha Sri Lanka

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Achievement: YOLOAchievement: Pull Sharkx2

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Achievement: YOLOAchievement: Pull Sharkx2

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Randikaviraj/README.md

Hi there, I am Randika 👋

I am a Computer Engineering undergraduate passionate about processor designing with HDLs, embedded systems, system engineering, software engineering, and backend technologies. A highly capable leader, having led multiple Senior class projects to completion. Proficient in a range of modern technologies.

  • 🔭 I’m currently working on Risc V SuperScalar Processor

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  1. e16-co502-RISCV-Pipeline-CPU-Implimentation-Group2 e16-co502-RISCV-Pipeline-CPU-Implimentation-Group2 Public

    Forked from cepdnaclk/e16-co502-RISCV-Pipeline-CPU-Implimentation-Group2

    This is the RISC-V ISA implementation by Group 2

    Verilog 1

  2. e16-3yp-automatic-fish-tank-control-system e16-3yp-automatic-fish-tank-control-system Public

    Forked from cepdnaclk/e16-3yp-automatic-fish-tank-control-system

    This is a third-year project by a group of students. Here we are developing a fish tank controlling device with a web app.

    Dart

  3. e16-CO328-Appointment-Scheduling-Software e16-CO328-Appointment-Scheduling-Software Public

    Forked from cepdnaclk/e16-CO328-Appointment-Scheduling-Software

    CO328 Software Engineering Project By Group 3

    Vue

  4. MIPS-single-cycle-Processor MIPS-single-cycle-Processor Public

    Verilog

  5. e16-4yp-Hardware-Cache-Switching-with-Operating-System-Context-Switches e16-4yp-Hardware-Cache-Switching-with-Operating-System-Context-Switches Public

    Forked from cepdnaclk/e16-4yp-Hardware-Cache-Switching-with-Operating-System-Context-Switches

    Verilog